We had an amazing technical discussion on Photonics in our latest episode of The Semiconductor Podcast featuring Dr. Prometheus Dasmahapatra, CTO at amPICQ and a global expert in photonics and semiconductor technologies 🌐🔬
Dr. Dasmahapatra’s journey spans some of the world’s leading research and industry organizations including ASML, imec, VTT Technical Research Centre of Finland, and Universitat Politècnica de València 🏭🏫. He is also the co-founder of iPronics Programmable Photonics, bringing deep insight into both cutting-edge research and deep-tech entrepreneurship 💡📡.
In this episode we have explored:
💡 What photonics is and why it is shaping the future of computing ⚡ The rise of silicon photonics and photonic integrated circuits 🔐🧠 Quantum-safe communication and technologies like Quantum Key Distribution (QKD) 🚀📊 The journey from research labs to deep-tech startups 🇮🇳🌏 Global photonics ecosystems and opportunities for India
As AI infrastructure 🤖, quantum technologies ⚛️, and secure communication 🔐 continue to evolve, photonics is emerging as a critical pillar of next-generation semiconductor innovation.
Running eSim Anywhere with Docker (Mac, Linux & Windows)
🎤 Guest & Presenter: Sumanto Kar
Docker installation :
🔹 What is eSim?
⚙️ A free and open-source Electronic Design Automation (EDA) tool (formerly Oscad/FreeEDA)
🧩 Integrated simulation environment built on tools like KiCad, Ngspice, GHDL, Verilator, and OpenModelica
🧪 Supports SkyWater SKY130 PDK for open-source chip design
📜 Released under the GNU GPL license
🔹 Focus of This Webinar
💻 In this session, we will demonstrate how Docker can simplify the installation and execution of eSim across multiple operating systems including MacOS, Linux, and Windows.
📦 Instead of complex toolchain setups, participants will learn how to run a ready-to-use eSim environment using containerization.
🔹 Why Attend?
🚀 Learn how Docker enables portable EDA environments across different operating systems
⚡ Avoid complicated installation steps and dependency issues
🖥️ Run eSim seamlessly on Mac, Linux, and Windows
📦 Understand how containerized EDA workflows support reproducible research and teaching
🎓 Ideal for students, educators, researchers, and hardware startups
🛠️ What Will Be Covered?
🐳 Introduction to Docker for EDA workflows
⚙️ Setting up a Docker-based eSim environment
💻 Running eSim on MacOS, Linux, and Windows using containers
📦 Managing simulation environments without dependency conflicts
🧪 Demonstration of running eSim simulations from a Docker container
📡 Best practices for portable semiconductor design environments
👥 Who Should Attend?
🎓 UG/PG Electronics Engineering Students (BSc/BTech/MSc/MTech/MS)
👨🏫 Faculty Members & Researchers
🔬 VLSI & Embedded Systems Enthusiasts
🧑🔧 Lab Instructors & Technical Staff
💡 Anyone interested in open-source semiconductor design tools
We have just dropped a special episode of The Semiconductor Podcast (TSP) featuring Venkatesh Kumar Pandurengan, General Manager of PTW Semiconductor India Private Limited , to discuss what Union Budget 2026 means for India’s semiconductor journey 🇮🇳
In this conversation, we explore the next phase of India’s semiconductor push — Semicon 2.0 and ISM 2.0 and what it could mean for manufacturing, ecosystem development, and talent.
💡 Key topics we covered:
📊 What Union Budget 2026 signals for semiconductor manufacturing in India
🔄 The transition toward Semicon 2.0 and ISM 2.0
🏭 The future of Fab, ATMP, and OSAT manufacturing in India
🔗 Building a strong semiconductor ecosystem and supply chain
👩🔬👨💻 The skills and talent pool needed to support this growth
🚀 Opportunities for MSMEs, startups, and ecosystem players
🌏 The potential for Eastern India to contribute to the semiconductor ecosystem
This episode brings together insights on policy, manufacturing, skills, and ecosystem development — essential for anyone following India’s semiconductor ambitions.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Venkatesh Kumar Pandurengan
Venkatesh Kumar Pandurengan is a seasoned practice leader with over 20 years of experience in semiconductor equipment engineering, operations, and engineering R&D services, spanning fabs, ATMP, and OSAT manufacturing environments. His expertise covers a wide range of process modules including ATMP/OSAT operations, CVD, PVD, ALD, Etch, Metrology, CMP, wafer handling, and quality systems. Venkatesh has worked across leading ATMP and OSAT ecosystems with organizations such as HCL Technologies (Sankalp Semiconductors), Infineon Singapore, and ASE Singapore, as well as global fabs including IM Flash Singapore, Micron Singapore, Intel, GlobalFoundries, Tower Semiconductors, Semiconductor Laboratory (SCL) Mohali, and META. He also brings deep engagement with major semiconductor equipment OEMs such as Applied Materials, Lam Research, Tokyo Electron (TEL), KLA, Agilent, and Teradyne (including J750 platforms), along with their sub-assembly units, making him a well-rounded leader with end-to-end insight into the semiconductor manufacturing value chain.
Once upon a time, networking meant configuring switches manually and managing small server racks. Today, AI runs on massive hyperscale data centers powered by automation, observability, and intelligent networking.
In this episode of The Semiconductor Podcast (TSP), we shift our mindset across generations of technology:
🔹 How server room networking evolved from DotCom era to AI-era data centers
🔹 Why data centers — not just AI models — are the real foundation of AI 🤖
🔹 How AI workloads changed networking architectures (Leaf–Spine, Disaggregation)
🔹 Why automation is no longer optional ⚙️
🔹 How CCNA & MCSE skills are evolving beyond traditional roles
🔹 What modern engineers must learn to stay relevant in AI-first infrastructure
💡 Inspired by real industry insights into modern networking, automation, and AI-driven operations.
👨💻 If you are an engineer, student, or tech enthusiast asking:
👉 “How should my career evolve in the AI era?”
This episode gives you the roadmap.
🎧 Watch now and rethink networking for the AI age.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape.
Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Verlaine J Muhungu
Verlaine J Muhungu is a Network Engineer and Technical Writer with over a decade of experience spanning routing & switching, network automation, APIs, and secure multi-vendor architectures. Specializing in modern, AI-driven networking, he works at the intersection of software, automation, observability, and traditional infrastructure—leveraging Python, pyATS, Cisco APIs (Meraki, Webex, Duo), ThousandEyes, and agentic AI systems to design scalable, automation-first networks. Currently serving as Technology Advisor at NexLink and Founder of DoDo Botics, he also contributes globally as a technology writer with Informa TechTarget, and publishes educational content through platforms such as HackerNoon and the Cisco Learning Network. A future Cisco Press author and DevNet advocate, Verlaine champions continuous learning, believing that AI doesn’t replace network engineers—it amplifies those who keep building, automating, and shipping.
Watch the episode here :
Today on The Semiconductor Podcast, we’re honored to feature Dr. Veena Chakravarthi,Director of Research & Engineering , LeadSoc Technologies Pvt Ltd and a semiconductor industry veteran with 38+ years of experience across VLSI, SoC architecture, research, startups, and academia.
In this powerful and deeply insightful episode, Dr. Veena Chakravarthi shares:
🚀 Her journey into VLSI & SoC design when India’s semiconductor ecosystem was still nascent
🧭 How semiconductor leadership has evolved over the past two decades
🧠 Real-world challenges in SoC architecture, low-power design, and IP-led innovation
🏗️ Building and scaling high-performance Offshore Development Centers (ODCs)
🎓 Bridging industry and academia as a professor, mentor, and researcher
📘 The story behind her widely referenced book A Practical Approach to VLSI SoC Design
🌸 A special early Women’s Day conversation on navigating deep tech as a woman leader, retaining women talent, and inspiring the next generation 🌷
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Dr. Veena Chakravarthi
Dr. Veena Chakravarthi is a semiconductor industry veteran with over 38 years of experience spanning VLSI and SoC architecture, design methodology, low-power systems, and end-to-end silicon realization. She currently serves as Director (Research & Engineering) at LeadSoc Technologies, where she drives research-led innovation, leads offshore development center (ODC) setup and scaling for global clients, and focuses on customer engagement, IP development, and SoC architecture definition. Her distinguished career includes senior leadership roles at Synopsys, co-founding and serving as CTO of a medtech startup with multiple US and India patents, and heading research at a leading engineering institute, where she mentored PhD scholars and actively bridged academia–industry gaps. A respected educator and published author of A Practical Approach to VLSI SoC Design (2nd edition), Dr. Chakravarthi is widely admired for her deep technical expertise, strategic leadership, and passion for nurturing next-generation semiconductor talent
Abriviation of Design for Testability. A set of design techniques that make ICs more testable after manufacturing. Since testing each functionality manually is impractical, DFT ensures that defects can be efficiently detected, diagnosed using ATE.
Challenges in Testability of Digital Circuits :
For Combinational Logic, testability decreases with increasing logic levels, whereas Sequential Circuits are harder to test due to multiple internal states.
Why is DFT important?
DFT is crucial to -
i. detect manufacturing defects (shorts, opens, stuck-at faults)
ii . to reduce the cost and time of post-silicon testing
iii. to ensure high yield and reliability of chips in production.
iv. to enable in-system diagnostics (like built-in self-test/BIST)
Common DFT Techniques :
i. Scan Insertion / Scan Chains :Converts flip-flops into a shift-register structure, increase controllability and observability, Enables automatic generation of test patterns (ATPG – Automatic Test Pattern Generation).
ii. Boundary Scan (IEEE 1149.1 / JTAG) : Adds test circuitry to I/O pads for board-level testing and debugging. Common in SoCs and PCBs.
iii. Built-In Self-Test (BIST) : Circuit tests itself using internally generated patterns and response checking. Includes LBIST i.e. Logic BIST, MBIST Memory BIST
iv. Memory BIST (MBIST) : Specifically targets SRAM/DRAM/Flash testing inside the chip. Applies march tests or algorithms to detect memory faults.
v. Compresses test patterns and decompresses them on-chip to reduce test time and memory usage
vi. Test Compression : Compresses test patterns and decompresses them on-chip to reduce test time and memory usage
vii. Fault Simulation and ATPG : Software tools simulate faults and generate efficient test vectors
DFT Approaches :
1. Ad Hoc Approach
2. Structured Approach
DFT : Ad-hoc Approach
What is Ad-hoc approach ?
Non-systematic manual methods used in the early stages of test design, served as an early method to improve testability. This approach is limited in scalability, predictability, and automation. This limitation led to the development of structured DFT techniques.
Key Characteristics of Ad-hoc DFT:
i. Local Modifications:Involves small, manual changes to specific parts of the circuit to enhance testability. Examples: adding test points, simplifying logic, breaking feedback loops.
ii. Non-Systematic:There is no formal or repeatable process. Every design requires a different ad-hoc strategy, often reinventing solutions.
iii. Unpredictable Results:Improvement in testability is not guaranteed or consistent. Effectiveness varies from design to design.
iv. Not Easily Automatable: Because of its manual and unstructured nature, it cannot be automated by EDA tools.
v. Difficult to Budget and Plan:Hard to estimate time, cost, or resources required to implement DFT using ad-hoc methods.
Limitations :
Poor scalability. Doesn’t work well for complex and large designs. Requires expert knowledge and deep understanding of the circuit. Difficult to maintain or reuse in future designs.
Test Point Insertion:
A widely used ad hoc DFT technique , improves controllability and observability of internal circuit node.
Process :
Low controllability/observability nodes are identified by Testability analysis. Test points are inserted at these nodes in the form of:
1. Observation Points (OPs) – to improve observability.
2. Control Points (CPs) – to improve controllability.
Observation Point (OP) Insertion:
Above figure illustrates a circuit. With 3 low-observability nodes - Observation points composed of a MUX and a D flip flop . Low observability node is connected to the 0 port of the MUX. All OPs are serially connected to form a shift register. SE signal is used for MUX post selection.
i. When SE = 1 and CK =1 : the logic values of the low-observability nodes are captured into the D-FFS
ii. When SE= 1 , OP1 , OP2 ,OP3 operate as a shift registers
Captured logic values can be observed through OP_output during sequential clock cycles. Observability of the circuit nodes is greatly improved.
Control Point Insertion:
Above figure illustrates a circuit with 3 low-controllability nodes.
Structure of Control Point: Composed of a MUX and a D flip-flop. The original node connection is replaced by inserting a MUX between source and destination to increase controllability of the point.
Operation:
i. Normal mode : Test Mode = 0. Source drives destination via MUX port 0.
ii. Test mode : Test Mode =1, Value from the D FF drives destination via MUX port 1.
Outcome: Controllability is greatly enhanced.
Caution: Avoid inserting CPs on critical paths to prevent extra delay.
Preferred Practice :
Instead of a CP alone, consider a scan point (combination of CP + OP). This allows observing the source end as well as controlling the destination.
Test point sharing:
Multiple nodes can share a test point using XOR gate networks to merge low-observability nodes. This can reduce area overhead but might increase routing complexity.
DFT : Structured DFT
Structured Design-for-Testability (DFT) aims to improve circuit testability through a methodical, test-oriented design methodology, yielding more predictable results. Scan Design is the most widely used structured DFT technique. Improves controllability and observability of storage elements in sequential circuits. Achieved by converting a sequential design into a scan design with three modes of operation:
1. Normal Mode : All test signals are off; the circuit works in its functional configuration.
2. Shift Mode : Used to shift test data into and out of scan cells.
3. Capture Mode : Used to capture test responses after applying test stimuli.
Role of Test Mode Signal (TM) :
In Shift and Capture modes, the TM signal enables all test-related features. It simplifies testing, debugging, and fault diagnosis, improves fault coverage, Ensures safe circuit operation during tests. Circuit modes and operations are managed through extra test signals or test clocks.
Sequential Circuit Testing and Scan Design :
Testing sequential circuit is difficult. Sequential circuit has to low controllability and observability of internal states.Scan design provides external access to selected storage elements
- Selected storage element is converted into scan cells
- Scan cells are connected as scan chains (shift registers)
- In shift mode, test data is shifted in and responses are shifted out in n clock cycles.
- Direct access to storage elements simplifies test generation and speeds up fault detection.
SCAN CELL DESIGN:
A scan cell typically has two selectable inputs:
i. Data Input (DI): Receives signals from the circuit’s
combinational logic.
ii. Scan Input (SI): Receives signals from the output of
another scan cell to form one or more scan chains.
Converting Normal Flop into Scan Flop:
- A normal D-FF is converted in to a scan flop
- SCAN input is multiplex before putting into scan chain
- Scan enable is used to control which input will
propagate to output
Formation of Scan Chains :
- Scan cells are linked in sequence
- First scan cell’s scan I/P is connected to a primary I/P
- Last scan cell’s O/P is connected to a primary O/P
Selection Mechanism for Modes :
- Normal/Capture Mode: Data input is selected to update the output.
- Shift Mode: Scan input is selected to update the output.
Various Scan Cell Design :
1. Muxed-D Scan
2. Clocked-Scan
3. Level-Sensitive Scan Design (LSSD)
1. MUXED D-SCAN CELL:
i. Edge- triggered muxed-D scan cell design :
This scan cell is composed of a D flip-flop and a multiplexer. The multiplexer uses a scan enable (SE) input to select between the data input (DI) and the scan input (SI). In normal/capture mode, SE is set to 0. The value present at the data input DI is captured into the internal D flip-flop when a rising clock edge is applied. In shift mode, SE is set to 1. The SI is now used to shift in new data to the D flip-flop while the content of the D flip-flop is being shifted out.
ii. Level-sensitive/edge-triggered muxed-D scan cell design :
This scan cell is composed of a multiplexer, a D latch, and a D flip-flop. The multiplexer uses a scan enable input SE to select between the DI and SI. Shift operation is conducted in an edge-triggered manner . Normal and capture operation are conducted in a level-sensitive manner. Major advantages of using muxed-D scan cells are their compatibility to modern designs. The disadvantage is that each muxed-D scan cell adds a multiplexer delay to the functional path.
2. CLOCKED SCAN CELL :
An edge-triggered clocked-scan cell can also be used to replace a D flip-flop in a scan design. A clocked-scan cell also has a data input DI and a scan input SI . In the clocked-scan cell, input selection is conducted using two independent clocks, data clock DCK and shift clock SCK .
Normal/capture mode : The data clock DCK is used to capture the value present at the data input DI into the clocked-scan cell.
Shift Mode : The shift clock SCK is used to shift in new data from the scan input SI into the clocked-scan cell, while the current content of the clocked- scan cell is being shifted out.
The major advantage of using a clocked-scan cell is that it results in no performance degradation on the data input.
The major disadvantage, however, is that it requires additional shift clock routing.
3. LSSD SCAN CELL DESIGN:
LSSD scan cell is used for level-sensitive, latch-based design.
Above figure shows a polarity-hold shift register latch (SRL) design, that can be used as an LSSD scan cell.
This scan cell contains two latches, a master two-port D latch L1 and a slave D latch L2 . Clocks C, A, and B are used to select between the data input D and the scan input I to drive L1 and L2 . In an LSSD design, either L1 or L2 can be used to drive the combinational logic of the design.
In order to guarantee race-free operation, clocks A, B, and C are applied in a non-overlapping manner.
In designs where +L1 is used to drive the combinational logic, the master latch L1 uses the system clock C to latch system data from the data input D and to output this data onto +L1.
In designs where +L2 is used to drive the combinational logic, clock B is used after clock A to latch the system data from latch L1 and to output this data onto +L2.
Capture mode uses both clocks C and B to output system data onto L2 . The major advantage of using an LSSD scan cell is that it allows us to insert scan into a latch-based design. In addition, designs using LSSD are guaranteed to be race-free, which is not the case for muxed-D scan and clocked-scan designs. The major disadvantage, however, is that the
technique requires routing for the additional clocks, which increases routing complexity.
In our latest episode of The Semiconductor Podcast, we sit down with Parikshit Sengupta, Segment Head – Materials & Semiconductor at HORIBA India, to explore India’s evolving semiconductor manufacturing journey.
🔍 From his personal journey into semiconductors to a deep, yet accessible discussion on:
🧪 Materials, characterization & process control
🏭 What a full-grown semiconductor manufacturing ecosystem really looks like
🌍 How India’s trajectory compares with the West and the East
📊 The role of long-term policy continuity in shaping semiconductors
🎓 Academia–industry collaboration & skill development
👩🔧 And most importantly — practical guidance for freshers aspiring to enter semiconductor manufacturing
This episode is a must-watch for students, engineers, professionals, and ecosystem builders who want to understand where India stands today and what lies ahead in the next decade.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Pariskshit Sengupta
Parikshit Sengupta is a seasoned semiconductor and scientific business leader with close to two decades of experience managing end-to-end operations across sales, service, manufacturing, applications, new product development, and business strategy. Currently serving as Segment Head – Materials & Semiconductor at HORIBA India, he has played a pivotal role in expanding the company’s semiconductor business across India and export markets, including successfully building the Export Division from the ground up. Known for his performance-driven mindset and collaborative leadership style, Parikshit consistently translates organizational goals into measurable outcomes. His expertise spans consultative and direct sales, new business development, distributor and account management, marketing, P&L ownership, and team leadership, making him a respected voice in India’s evolving semiconductor manufacturing and scientific instrumentation ecosystem.
We’re delighted to welcome Naveen Muddu Krishna , Director of Product Engineering, SanDisk to The Semiconductor Podcast for a deeply insightful and heartfelt conversation.
With over 22 years in the semiconductor industry, his journey is one that truly resonates—from hands-on engineering in digital, analog, and system design to leading large global teams across India, the US, South Korea, and Israel. In this episode, he speaks candidly about growth, responsibility, leadership, and the realities of building world-class products at scale.
🔍 What we explored in this episode:
• 🌱 His early career journey and lessons that shaped him as an engineer and leader • 🔄 Transitioning from technical contributor to global engineering leadership • 🌍 Leading diverse teams across geographies with trust and alignment • 🧠 Thinking at the system level across networking, embedded, video, healthcare, storage & defense • 🏭 Bridging the gap between design intent and manufacturing reality • 🤖 How AI, automation, and Industry 4.0 are reshaping engineering work • ⚖️ Where human judgment, accountability, and ownership still matter most • 🇮🇳 India’s evolving role in ESDM, GCCs, and global product ownership • 🎓 Closing the gap between industry and academia • 💬 Honest advice for Gen Z engineers navigating their careers
🎧 This episode is reflective, practical, and inspiring—especially for engineers, leaders, and anyone building long-term impact in deep tech.
We’re excited to announce a brand-new episode featuring Prof. Amlan Chakrabarti—a pioneer in quantum computing and a leading voice in VLSI, EDA, AI, and advanced computing.
In this episode, we explore his remarkable journey from hands-on EDA engineering to starting quantum computing research nearly two decades ago, well before it became mainstream. From developing early computational tools for quantum research to now looking at collaborations on qubit fabrication, the conversation truly spans the full stack—from design to devices.
🔍 What we discussed in today’s episode:
• 🧩 His early career in EDA (OrCAD, VHDL) and how it shaped his research mindset
• ⚛️ Why he chose quantum computing when it was still a niche field
• 🛠️ Key bottlenecks in quantum tech: hardware, CAD tools & algorithms
• 🔋 The role of reversible logic & ultra-low-power computing in future chips
• 📐 Gaps between academic EDA research and industry-ready tools
• 🔁 Where FPGAs and reconfigurable platforms fit in the next decade
• 🤖 How AI is becoming deeply embedded into chips and real-world systems
• 🇮🇳 Urgent gaps in India’s engineering education & research ecosystem
• 🎓 Skills young engineers & PhD aspirants need for semiconductors + AI + quantum
• 🌍 What excites him most about the next decade of computing and India’s global role
🎧 A deep, insightful, and future-facing conversation you don’t want to miss!
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Amlan Chakrabarti
Prof. Amlan Chakrabarti is a distinguished academic and researcher with over 20 years of experience in engineering education and research. He serves as the Chief Coordinator of the International Center of Excellence for Data Science, Artificial Intelligence, and Futuristic Technologies—an initiative of the Department of Higher Education, Government of West Bengal—driving innovation, collaboration, and global impact through advanced research and education. A Professor and Director of the A.K. Choudhury School of IT, University of Calcutta, and Adjunct Professor at IIIT Delhi, his core expertise spans quantum computing, machine learning, computer vision, cyber-physical systems, and reconfigurable computing. He completed his Ph.D. in quantum computing at the University of Calcutta and post-doctoral research at Princeton University, and has been recognized with several prestigious honors including the Young Scientist Award, BOYSCAST Fellowship, and Senior Member of IEEE status. Prof. Chakrabarti has authored over 200 research publications and has successfully secured multiple national and international research grants.
This TSW (The Semiconductor Webinar) goes beyond textbook crystal growth theory and focuses on how ingots are actually prepared in semiconductor fabs. We will discuss industrial-scale ingot preparation methods—why certain methods are chosen, what process trade-offs fabs care about, and how quality, yield, cost, and scalability drive real decisions.
The session is industry-oriented, covering practical insights into methods such as CZ, MCZ, FZ, and specialty approaches, with emphasis industry inclined topics, rarely explained in academic courses.
Designed for students, fresh graduates, and professionals aiming to work in fabs, this webinar bridges the gap between theory and manufacturing reality, helping you understand how upstream wafer decisions impact downstream device performance and yield.
Who should attend:
* Aspiring fab engineers & process engineers
* VLSI / semiconductor students preparing for industry roles
* Professionals transitioning from EDA/design to manufacturing
* Anyone who wants a fab-floor perspective, not textbook slides
If you want to understand how fabs think, not just how books explain—this session is for you.
Guests Bio :
1. Bhavesh Motwani :
Bhavesh Motwani is currently being enrolled in the MTech program in Semiconductor Technology at Nirma University. He is being trained as an intern at Monk9 Technology, where hands-on experience in semiconductor fabrication is being gained. His BTech degree in Electronics and Communication Engineering was completed at GEC Bharuch, affiliated with Gujarat Technological University.
His initial interest in the field of Electronics and Communication was sparked by work in robotics and embedded systems. Several projects were undertaken using platforms like MSP430, Arduino, and ESP boards. Through this exploration, deeper curiosity about the internal working of these systems was developed, eventually leading him toward the field of VLSI and semiconductors.
Due to limited lab access and software tools at his government college, Bhavesh was encouraged by a professor to pursue MTech at a reputed institution. At Nirma University, inspiration was drawn from Dr. N.M. Devashrayee, whose teaching in semiconductor fabrication and physics encouraged him to explore the domain in depth.
This interest marked the beginning of his journey into semiconductor fabrication, packaging, assembly, and testing. As India’s semiconductor ecosystem continues to expand, Bhavesh is determined to contribute meaningfully and aspires to take on a leadership role in advancing the industry.
Jayshree Adwani :
Jayshree Adwani is currently being enrolled in the second year of the MTech program in Semiconductor Technology at Nirma University. She is undergoing internship training at MONK9, with a focus on the semiconductor fabrication domain. Her interest in semiconductors was cultivated during her undergraduate studies in Electronics and Communication Engineering at Charusat University. A six-month internship was completed at VERIFAST Technologies, which later transitioned into a full-time role where she worked for one year in the verification domain.
While experience in verification and familiarity with communication protocols was gained, a stronger inclination toward fabrication was gradually developed. The ability to transform theoretical knowledge into physical semiconductor devices inspired her to pursue further studies focused on fabrication.
Throughout her MTech program, comprehensive knowledge has been acquired in semiconductor physics, cleanroom processes, and fabrication flow — covering wafer processing, device physics, and IC manufacturing. This hands-on exposure has deepened her passion and expertise in the field.
At Nirma University, Jayshree has also been actively involved in facilitating connections between academia and industry. Internship opportunities have been sought independently by her, both during and after her time at VERIFAST. She remains committed to contributing to India’s semiconductor growth and envisions herself playing a key role in this transformative industry.
Watch the webinar here :
