Isolation Cell In VLSI

In this article we will discuss about Isolation Cell and their importance in VLSI. Once completed you will able to answer the following questions:

1. What are isolation cell and why they are important?

2. How many types of isolation cells are there in commercial 

    standard library?

3. Why an isolation cell is bare necessary in a multiple power        domain chip?

4. How Isolation cell is associated with power aware RTL       

    verification?

Power Management Methods:

In a state-of-art chip power management inside the IC is done in several different ways. Lets take a brief look on such methods. First in the list is using multiple threshold voltages or Multi Vt. Next comes using multiple VDDs for multiple domain in the same chip. We use power gating method for managing the power between two different blocks in the same chip. We use clock gating for clock cells. Dynamic Voltage scaling and Dynamic Frequency Scaling are two other methods used for power management. Different standard cells like Retention Flop/Cell , Isolation Cell , Power Switch Cell,  Level Shifter Cell are used for power management in a chip. 

Problem Scenario Among Power Domains :

Fig. 1 : Power domains  

Inter-domain signals can become complicated if the connecting interface changes during different power modes. During Power Gating operation, the circuit will contain few ON domains and few OFF domains together at any point of time. In such situation, output of a OFF domain sends invalid signal to the ON Domain.

When this floating voltage is propagated to the inputs of the receiving end, a short-circuit current is produced. Crowbar Current may flow because output pins of OFF domain might be in the meta- stable/dangling state.

Isolation Cell To The Rescue : 

To deal with such problematic situation specially designed Standard Cell (a.k.a Isolation Cell) is placed between power gated block and the active block. An Isolation Cell clamps the signal at its input pin to a defined known state, either logic "0 ‟ or logic "1". Hence transmission of invalid signal is eradicated. Controllers are used to control and synchronize local power switches and isolation cells with clock gating or power gating signals.

                              Fig. 2 : Importance of Isolation Cell   

Two types of controllers are used in VLSI :

i.  Simple adaptive controller

ii. Enhanced adaptive controller

Isolation Method and Isolation Cell:

                                  Fig. 3 :  Isolation Cell  

When Power Gating method is applied to a design, in a particular mode of operation, we might end up with few ON domains and few OFF domains. If the outputs of the Shutdown domain are connected to the Active Part of the design, then it might lead to Invalid Signal Transmission and crowbar current as a result. To avoid this, an Isolation Cell is placed on the output nets of Switched OFF domains interacting with an Active  Portion of the Design.

Detection of Missing Isolators :

                                   Fig. 4 : Missing Isolators 

The isolation and level shifter strategies  are defined at RTL stage itself in UPF/CPF  file. In UPF/CPF if an isolation and/or level shifter strategy is to be defined between power nets connected to source and sink  domains. Unable to do so the resulting in malfunctioning of the design. Such  scenarios are detected by standard EDA  tools and an error is flagged.

Isolation Standard Cell Example : 

Fig. 5 : Isolators Standard Cell

Drawbacks & Improvements :

                          Fig. 6 : Isolation Cell and Level Shifters

Isolation cells need to be inserted at the interface of different power domains. This adds significant area and power overhead. The AND/OR isolation cells, require more area. To lower the area overhead, the isolation cells use an NMOS pull-down transistor. Using high VT transistors further lowers the leakage current caused by the inactive isolation cells.

So that was all about Isolation Cells. Now lets summarize what we have discussed here :

Conventional techniques are applied to perform electrical checks for voltage crossing domains and power islands. Voltage level shifter, electrical isolation cells, retention cell etc are applied in through Power Aware RTL using CPF/UPF. Isolation cells (ISO) enable electrically safe power shutdown states from affecting powered-on regions, by fencing off the propagation of non-deterministic logic states.Two types of Standard Cells isolators are used : OR/AND Types.

Watch the video lecture here :

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