What is DFT ?
Abriviation of Design for Testability. A set of design techniques that make ICs more testable after manufacturing. Since testing each functionality manually is impractical, DFT ensures that defects can be efficiently detected, diagnosed using ATE.
Challenges in Testability of Digital Circuits :
For Combinational Logic, testability decreases with increasing logic levels, whereas Sequential Circuits are harder to test due to multiple internal states.
Why is DFT important?
DFT is crucial to -
i. detect manufacturing defects (shorts, opens, stuck-at faults)
ii . to reduce the cost and time of post-silicon testing
iii. to ensure high yield and reliability of chips in production.
iv. to enable in-system diagnostics (like built-in self-test/BIST)
Common DFT Techniques :
i. Scan Insertion / Scan Chains : Converts flip-flops into a shift-register structure, increase controllability and observability, Enables automatic generation of test patterns (ATPG – Automatic Test Pattern Generation).
ii. Boundary Scan (IEEE 1149.1 / JTAG) : Adds test circuitry to I/O pads for board-level testing and debugging. Common in SoCs and PCBs.
iii. Built-In Self-Test (BIST) : Circuit tests itself using internally generated patterns and response checking. Includes LBIST i.e. Logic BIST, MBIST Memory BIST
iv. Memory BIST (MBIST) : Specifically targets SRAM/DRAM/Flash testing inside the chip. Applies march tests or algorithms to detect memory faults.
v. Compresses test patterns and decompresses them on-chip to reduce test time and memory usage
vi. Test Compression : Compresses test patterns and decompresses them on-chip to reduce test time and memory usage
vii. Fault Simulation and ATPG : Software tools simulate faults and generate efficient test vectors
DFT Approaches :
1. Ad Hoc Approach
2. Structured Approach
DFT : Ad-hoc Approach
What is Ad-hoc approach ?
Non-systematic manual methods used in the early stages of test design, served as an early method to improve testability. This approach is limited in scalability, predictability, and automation. This limitation led to the development of structured DFT techniques.
Key Characteristics of Ad-hoc DFT:
i. Local Modifications: Involves small, manual changes to specific parts of the circuit to enhance testability. Examples: adding test points, simplifying logic, breaking feedback loops.
ii. Non-Systematic: There is no formal or repeatable process. Every design requires a different ad-hoc strategy, often reinventing solutions.
iii. Unpredictable Results: Improvement in testability is not guaranteed or consistent. Effectiveness varies from design to design.
iv. Not Easily Automatable: Because of its manual and unstructured nature, it cannot be automated by EDA tools.
v. Difficult to Budget and Plan: Hard to estimate time, cost, or resources required to implement DFT using ad-hoc methods.
Limitations :
Poor scalability. Doesn’t work well for complex and large designs. Requires expert knowledge and deep understanding of the circuit. Difficult to maintain or reuse in future designs.
Test Point Insertion:
A widely used ad hoc DFT technique , improves controllability and observability of internal circuit node.
Process :
Low controllability/observability nodes are identified by Testability analysis. Test points are inserted at these nodes in the form of:
1. Observation Points (OPs) – to improve observability.
2. Control Points (CPs) – to improve controllability.
Observation Point (OP) Insertion:
Above figure illustrates a circuit. With 3 low-observability nodes - Observation points composed of a MUX and a D flip flop . Low observability node is connected to the 0 port of the MUX. All OPs are serially connected to form a shift register. SE signal is used for MUX post selection.
i. When SE = 1 and CK =1 : the logic values of the low-observability nodes are captured into the D-FFS
ii. When SE= 1 , OP1 , OP2 ,OP3 operate as a shift registers
Captured logic values can be observed through OP_output during sequential clock cycles. Observability of the circuit nodes is greatly improved.
Control Point Insertion:
Above figure illustrates a circuit with 3 low-controllability nodes.
Structure of Control Point: Composed of a MUX and a D flip-flop. The original node connection is replaced by inserting a MUX between source and destination to increase controllability of the point.
Operation:
i. Normal mode : Test Mode = 0. Source drives destination via MUX port 0.
ii. Test mode : Test Mode =1, Value from the D FF drives destination via MUX port 1.
Outcome: Controllability is greatly enhanced.
Caution: Avoid inserting CPs on critical paths to prevent extra delay.
Preferred Practice :
Instead of a CP alone, consider a scan point (combination of CP + OP). This allows observing the source end as well as controlling the destination.
Test point sharing:
Multiple nodes can share a test point using XOR gate networks to merge low-observability nodes. This can reduce area overhead but might increase routing complexity.
DFT : Structured DFT
Structured Design-for-Testability (DFT) aims to improve circuit testability through a methodical, test-oriented design methodology, yielding more predictable results. Scan Design is the most widely used structured DFT technique. Improves controllability and observability of storage elements in sequential circuits. Achieved by converting a sequential design into a scan design with three modes of operation:
1. Normal Mode : All test signals are off; the circuit works in its functional configuration.
2. Shift Mode : Used to shift test data into and out of scan cells.
3. Capture Mode : Used to capture test responses after applying test stimuli.
Role of Test Mode Signal (TM) :
In Shift and Capture modes, the TM signal enables all test-related features. It simplifies testing, debugging, and fault diagnosis, improves fault coverage, Ensures safe circuit operation during tests. Circuit modes and operations are managed through extra test signals or test clocks.
Sequential Circuit Testing and Scan Design :
Testing sequential circuit is difficult. Sequential circuit has to low controllability and observability of internal states.Scan design provides external access to selected storage elements
- Selected storage element is converted into scan cells
- Scan cells are connected as scan chains (shift registers)
- In shift mode, test data is shifted in and responses are shifted out in n clock cycles.
- Direct access to storage elements simplifies test generation and speeds up fault detection.
SCAN CELL DESIGN:
A scan cell typically has two selectable inputs:
i. Data Input (DI): Receives signals from the circuit’s
combinational logic.
ii. Scan Input (SI): Receives signals from the output of
another scan cell to form one or more scan chains.
Converting Normal Flop into Scan Flop:
- A normal D-FF is converted in to a scan flop
- SCAN input is multiplex before putting into scan chain
- Scan enable is used to control which input will
propagate to output
Formation of Scan Chains :
- Scan cells are linked in sequence
- First scan cell’s scan I/P is connected to a primary I/P
- Last scan cell’s O/P is connected to a primary O/P
Selection Mechanism for Modes :
- Normal/Capture Mode: Data input is selected to update the output.
- Shift Mode: Scan input is selected to update the output.
Various Scan Cell Design :
1. Muxed-D Scan
2. Clocked-Scan
3. Level-Sensitive Scan Design (LSSD)
1. MUXED D-SCAN CELL:
i. Edge- triggered muxed-D scan cell design :
This scan cell is composed of a D flip-flop and a multiplexer. The multiplexer uses a scan enable (SE) input to select between the data input (DI) and the scan input (SI). In normal/capture mode, SE is set to 0. The value present at the data input DI is captured into the internal D flip-flop when a rising clock edge is applied. In shift mode, SE is set to 1. The SI is now used to shift in new data to the D flip-flop while the content of the D flip-flop is being shifted out.
ii. Level-sensitive/edge-triggered muxed-D scan cell design :
This scan cell is composed of a multiplexer, a D latch, and a D flip-flop. The multiplexer uses a scan enable input SE to select between the DI and SI. Shift operation is conducted in an edge-triggered manner . Normal and capture operation are conducted in a level-sensitive manner. Major advantages of using muxed-D scan cells are their compatibility to modern designs. The disadvantage is that each muxed-D scan cell adds a multiplexer delay to the functional path.
2. CLOCKED SCAN CELL :
An edge-triggered clocked-scan cell can also be used to replace a D flip-flop in a scan design. A clocked-scan cell also has a data input DI and a scan input SI . In the clocked-scan cell, input selection is conducted using two independent clocks, data clock DCK and shift clock SCK .
