In this article , we break down Testability Analysis in digital circuits in a simple and practical way. Learn how controllability and observability define how easy it is to test internal signals from primary inputs and outputs. We also introduce SCOAP, a widely used method that assigns numerical values to measure testability. The video covers both combinational and sequential aspects, along with how these metrics guide test generation and design improvements. If you're working in VLSI, DFT, or chip design, this episode will help you understand how to identify and improve poorly testable areas in your design.
- Assumes only primary inputs (PIs) can be directly controlled
- Assumes only primary outputs (POs) can be directly observed
Testability reflects:
- Effort to control internal signals from PIs and effort to observe internal signals at POs
Testability Analysis:
- Testability analysis assigns numerical values to each signal in a circuit. It helps during test generation, such as choosing the easiest signal to control. It identifies poorly testable areas for improvement using test point insertion.
Why it matters:
Guides test generation decisions. Identifies poorly testable areas in a design. Supports testability enhancement (e.g., test point insertion). Enables early detection of testability issues during design stages. SCOAP is a popular topology-based testability analysis method.
Since the 1970s, engineers have developed ways to check how easy a circuit is to test. SCOAP was the first popular method to measure testability using circuit structure
SCOAP introduced two key ideas:
1. Controllability → How hard it is to set a signal to 0 or 1
2. Observability → How hard it is to see a signal at the output
SCOAP metrics are later used to decide where to add test points. Traditional testability works at the gate level, using circuit connections.
Two common approaches:
- Topology / Probability based → Fast but sometimes inaccurate
- Simulation based → More accurate but slower
Accuracy reduces when signals split and rejoin (reconvergent fanout). Today’s chips need testability checks at RTL level, not just gate level.
What is SCOAP?
- SCOAP (Sandia Controllability & Observability Analysis Program) is a method to measure how easy or hard it is to test a signal inside a digital circuit.
SCOAP Calculates 6 Values for Each Signal
1. Combinational (No Clock, Single Snapshot)
- CC0(s) → Ease of setting signal s to 0
- CC1(s) → Ease of setting signal s to 1
- CO(s) → Ease of observing s at the output
2. Sequential (With Clock Cycles)
- SC0(s) → Clock cycles needed to set s to 0
- SC1(s) → Clock cycles needed to set s to 1
- SO(s) → Clock cycles needed to observe s
Boundary Rules (Starting Points) :
1. Primary Input :
- CC0 = CC1 = 1 (easy to control)
- SC0 = SC1 = 0
2. Primary Output :
- CO = SO = 0 (easy to observe)
=> Lower value = easier to test
Controllability values: 1 → ∞
Observability values: 0 → ∞
CC – Combinational Controllability
CO – Combinational Observability
SC – Sequestioal Controllability
SO – Sequestioal Observability
Controllability & Observability Calculation
1. Combinational Controllability (CC):
Measures the difficulty of setting a signal to 0 (CC0) or 1 (CC1) through primary inputs. Computed from Primary Inputs (PI) → Primary Outputs (PO). Calculated level-by-level (breadth-first) through the combinational logic.
2. Combinational Observability (CO) :
Measures how difficult it is to observe a signal’s effect at a primary output. Computed from Primary Outputs (PO) → Primary Inputs (PI). Calculated level-by-level, ensuring downstream observability is known first.
3. Sequential Controllability (SC) :
Measures the difficulty of controlling flip-flop states through primary inputs across clock cycles. Extends combinational controllability by considering state transitions in sequential circuits. Includes the cost of clock cycles required to set flip-flop values.
4. Sequential Observability (SO) :
Measures the difficulty of observing flip-flop values at primary outputs over time. Extends combinational observability by considering state propagation through clock cycles
Controllability → PI → PO
Observability → PO → PI
Controllability Measures:
The figure shows a circuit consists of an AND gate and a positive-edge-triggered D-FF.
1. Controllability measures of Signal d :
- To control signal d to 0, either input a or b must be set to 0
- To control d to 1, both inputs a and b must be set to 1
CC0(d) = min{CC0(a),CC0(b)}+1
SC0(d) = min{SC0(a),SC0(b)}+1
CC1(d) = CC1(a) + CC1(b) + 1
2. Controllability measures of Signal q to 0 :
- To control the data output q of the D flip-flop to 0 ,
(i) data input d and the reset signal r can be set to 0 while applying a rising clock edge (a 0-to-1transition) to CK
(ii) r can be set to 1 while holding CK to 0. Alternatively, this can be accomplished by setting r to 1 while holding CK at 0
CC0(q) = min{CC0(d)+CC0(CK)+CC1(CK)+CC0(r),CC1(r)+CC0(CK)}
SC0(q) = min{SC0(d)+SC0(CK)+SC1(CK)+SC0(r)+1, SC1(r)+SC0(CK)}
3. Controllability measures of signal q to 1:
- To measure the data input d to 1 , reset signal r need to be set to o 0 while applying a rising clock edge to the CK
CC1(q) = CC1(d)+CC0(CK)+CC1(CK)+CC0(r)
SC1(q) = SC1(d)+SC0(CK)+SC1(CK)+SC0(r)+1
Observability Calculation:
1. Combinational and sequential observability measures of d:
- Signal d can be observed at q by holding the r at 0 , applying a rising clock edge to CK
CO(d) = CO(q) + CC0(CK) + CC1(CK)+ CC0(r)
SO(d) = SO(q) + SC0(CK) + SC1(CK)+ SC0(r) +1
Combinational and sequential observability measures of r:
- Signal r can be observed by first setting q to 1 and then holding CK at the inactive state 0
CO(r) = CO(q)+CC1(q)+CC0(CK)
SO(r) = SO(q)+SC1(q)+SC0(CK)
2. Observability measures of CK at q:
- set q to 1, r to 0, and d to 0 and apply a rising clock edge at CK
- set both q and r to 0, set d to 1, and apply a rising clock edge at CK
CO(CK) = CO(q)+CC0(CK)+CC1(CK)+CC0(r)+min{CC0(d)+CC1(q),CC1(d)+CC0(q)}
SO(CK)= SO(q)+SC0(CK)+SC1(CK)+SC0(r)+min{SC0(d)+SC1(q),SC1(d+SC0(q)}+1
3. Observability measures for both inputs a and b :
To observe an input of the AND gate at d requires setting the other input to 1
CO(a) = CO(d)+CC1(b)+1
SO(a) = SO(d)+SC1(b)
CO(b) = CO(d)+CC1(a)+1
SO(b) = SO(d)+SC1(a)
Watch the video lecture here:
