👥 Who Should Attend?
🎓 Students & Graduates exploring the world of digital logic design, RTL, and looking to build a career in VLSI and processor design. 💼 Early-career professionals eager to strengthen their Verilog and RTL simulation fundamentals. 🛠️ Engineers & Chip Designers wanting to deepen their knowledge in combinational logic and performance-driven shift operations. 💡 Tech Enthusiasts & Hobbyists interested in how efficient shift operations improve CPU and DSP speeds. 📚 Educators & Researchers seeking structured examples to teach advanced Verilog and computer architecture. 🔹 Why Attend? 📟 Basics of Microcontrollers and their role in IoT 🛠️ PCB fundamentals: layers, components, and terminologies 🔧 Key components like Atmega328p, CH340g chip, and ICSP headers ⚡ Power, communication, and programming interfaces 🖼️ Final PCB render and practical insights Guests Bio : Swastik Dey is currently pursuing his M.Tech in VLSI Design from the Institute of Radio Physics and Electronics, Calcutta University. He holds a B.Tech degree in Electronics and Communication Engineering from Techno Main Saltlake, Maulana Abdul Kalam Azad University of Technology. His academic interests include Embedded Systems, Internet of Things (IoT), and FPGA Systems, where he continues to explore innovative approaches to hardware and system design. 🎙️ New to streaming or looking to level up? Check out StreamYard and get ₹740 discount! 😍 https://streamyard.com/pal/d/5468382652137472
Watch the webinar episode here :
