We are thrilled to welcome Matthew Barsing, a cross-border investment strategist with 20+ years of experience in FDI, bilateral trade, and digital economy policy. Currently Director & CCO at EPS Consultants and Ambassador to IT Park Uzbekistan, Matthew is also the author of Unleashing Malaysia’s Economic Potential. 📖🇲🇾
In this episode of The Semiconductor Podcast (TSP), we have explored :
💼 Matthew’s journey — from diverse global roles to shaping Malaysia’s semiconductor strategy
📚 The making of his new book & his upcoming appearance at the Delhi Book Fair 🇮🇳
🏭 Malaysia’s semiconductor evolution — balancing traditional manufacturing with AI & deep-tech
🌐 India–Malaysia collaboration — as a gateway into ASEAN markets
🤝 Government incentives & leveraging the China+1 strategy for resilient supply chains
🎯 High-potential sectors — medical devices, automotive, AI chips, advanced packaging
👩💻 Talent development — driving Malaysia’s AI & semiconductor workforce growth
💡 Future vision — from joint R&D to a pan-Asian alliance for fabless startups
If you’re an entrepreneur, investor, or policymaker eyeing Malaysia’s growing role in the global semiconductor supply chain, this conversation is packed with insights you won’t want to miss.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Matthew Barsing
Matthew Barsing – Cross-Border Business & Tech Ecosystem Leader
Matthew is a global business strategist with over two decades of experience in foreign direct investment, AI, and technology ecosystem development across Asia and emerging markets. He serves as Chief Commercial Officer at EPS Consultants, driving talent and outsourcing solutions across Southeast Asia and Japan. As Ambassador to IT Park Uzbekistan and a member of Malaysia’s National AI Office Talent Group, Matthew champions AI adoption, talent development, and cross-border tech investments. He also mentors startups with Orbit Startups and has scaled ventures like Superceed and Igoroom, leading regional expansions and AI-powered innovations. Previously, as Head of FDI at Malaysia Digital Economy Corporation, he secured RM5.37B in global projects, attracting Fortune 500 firms and transforming Malaysia’s Shared Services & Outsourcing sector. Passionate about building synergies between ASEAN, South Asia, and frontier markets, Matthew focuses on advancing semiconductors, AI, and digital infrastructure for inclusive growth.
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This video also suggests:
Malaysia semiconductor industry growth 2025
Malaysia role in global semiconductor supply chain
India Malaysia semiconductor collaboration opportunities
ASEAN market entry strategy for Indian semiconductor startups
Foreign direct investment in Malaysia semiconductor sector
Government incentives for semiconductor investment in Malaysia
Malaysia AI and advanced semiconductor innovation
Balancing electronics manufacturing with AI in Malaysia
High-potential sectors in Malaysia semiconductor industry
China plus one strategy for semiconductor supply chain diversification
Talent development in Malaysia semiconductor and AI workforce
National AI Talent Working Group Malaysia impact
Cross-border partnerships in semiconductor and deep-tech
Gateway to ASEAN semiconductor markets via Malaysia
Malaysia–Australia trade in electronics and semiconductors
Pan-Asian alliance for fabless semiconductor startups
Joint R&D opportunities in ASEAN and India semiconductors
Financing options for cross-border hardware startups in Asia
Book on Malaysia economic potential by Matthew Barsing
Delhi Book Fair 2025 featured author Matthew Barsing
In this article we dive deep into the world of VLSI Testing and understand why it plays a crucial role in semiconductor manufacturing. Learn about the different test stages, the importance of fault coverage, and how yield and reject rates impact product quality. We explain test philosophies, verification testing, and the critical steps involved in post-fabrication chip debugging. Discover how manufacturing tests, testers, and test fixtures are used to ensure reliable product delivery while keeping cost considerations in mind. The video also covers silicon debugging, handling silicon failures, and the concept of Design for Manufacturability (DFM) to optimize chip performance and profitability. Perfect for students, engineers, and semiconductor enthusiasts!
Why VLSI Testing is Important?
Integrated Circuit (IC) or VLSI Testing includes procedures that is followed post fabrication in order to detect possible manufacturing defects. Testing is required to guarantee fault-free products A reliable product with small time to market will provide higher revenues than a second product with a greater time to market. Testing procedures at the minimum cost in time and resources are required!
Testing Necessity :
- Imperfections in fabrication process may lead to manufacturing defects.
- The manufacturing yield (Y) depends on used technology, silicon area and layout design.
- Decreasing feature size increases probability of defects during fabrication
- A single faulty transistor or wire results in faulty IC.
Why does a product fail test?
If a designed product fails in testing the probable reason might be any of the below :
(1) wrong testing procedure ,
(2) faulty fabrication process ,
(3) incorrect design ,
(4) faulty specification
The role of testing is to detect and determine exactly what went wrong. Correctness and effectiveness of testing is most important for quality products.
Testing is applying set of test stimuli to inputs of CUT and analyzing output responses.
(1) Incorrect O/P, CUT is faulty [FAIL]
(2) Correct O/P, CUT is fault-free [PASS]
VLSI Test Stages :
1. Verification testing, characterization testing and debug design :Verifies correctness of design and test procedure.
2. Manufacturing testing : Factory testing of all manufactured chips for parametric faults and for random defects.
3. Burn-in: Testing for reliability
4. Acceptance testing /incoming inspection : Customer performs tests on purchased parts to ensure quality.
Role of testing :
1. Detection: Go/no-go, is the chip fault-free/faulty. Must be fast.
2. Diagnosis:Determines whether the chip is faulty and investigate the reason of fault. Performed on chips that fail at detection level.
3. Device characterization: Determines and corrects error in design and/or test procedure.
4. Failure Analysis : Determines the manufacturing process errors that may have caused defects on the chip.
Yield , Reject Rate & Fault Coverage :
The yield of a manufacturing process is :
Two types of yield loss: Catastrophic and Parametric.
Catastrophic yield loss occurs is due to random defects and Parametric yield loss is due to process variations.
Inefficient testing may lead to undesirable situations like :
1. A faulty device appears to be a good part passing the test.
2. A good device fails the test and appears as faulty.
The reject rate provides an indication of the overall quality of the VLSI testing process.
Reject rate is also called Defect level.
Fault coverage of 100% is impossible because of the existence of undetectable faults. An undetectable fault means there is no test to distinguish the fault-free circuit from a faulty circuit containing that fault. Fault coverage can be modified and expressed as the fault detection efficiency or effective fault coverage:
Defect level = 1− yield^(1−fault coverage)
Test Philosophy :
Ideal Tests : Ideally detect all defects produced in a manufacturing process. Pass all functionally good chips, fail all defective chips. Large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects.
Real Tests : In reality due to design complexity of modern chip it is difficult to generate tests that detect every possible fault. Real Tests are based on analyzable fault models. Real Tests may not map to real defects. Some good chips are rejected and some bad chips are shipped.
Categories of Tests :
There are three main categories of test :
1. Logic Verification (Pre-Tapeout) : Ensures the circuit functions as intended. Performed before fabrication using simulations. Identifies logic bugs early.
2. Silicon Debug (Post-Fabrication): First batch of chips tested for functional correctness Helps debug issues at full system speed. Example: Testing a new processor on a prototype motherboard
3. Manufacturing Tests (Production) : Ensures every transistor, gate, storage element works. Conducted before shipping to customers . Identifies manufacturing defects .
Earlier detection means Lower cost . Testing must be thorough and proactive. Early detection of fault is very economical in IC design and manufacturing. A die/chip can be tested at different levels and we move forward testing cost increases.
Wafer Level : Detect defects early to reduce cost
Packaged Chip Level : Verify chip after packaging
Board Level : Test chips assembled on PCB
System Level : Check integration with other components
Field Level : Detect failures after deployment
Real-World Example:
Intel Pentium Bug (1994). A logic bug in the floating point divider went undetected 4 million faulty chips were shipped $450 million loss due to recall & reputation damage.
Most first-time silicon failures are due to design functionality issues. Testing must be planned early to,avoid costly mistakes. Debugging becomes harder post- fabrication due to limited visibility . Effective test strategies reduce cost & improve reliability.
Verification Testing in VLSI:
1.Verification Tests in the Design Process: Verification tests are usually the first ones a designer constructs. They check fundamental functionality, such as "Does the adder add?" or "Does the counter count?"
2. Equivalence Checking in Verification : Verification ensures that a synthesized gate-level description is functionally equivalent to the RTL. The goal is to also confirm that RTL aligns with the higher-level design specification.
3. The behavioral specification: The behavioral specification can be a verbal or textual description, a high-level language (C, SystemC, etc.), a hardware description language (VHDL, Verilog), a table of expected inputs and outputs, a golden model is often created as a reference for verification.
4. Functional equivalence : This step involve running simulations at different abstraction levels and comparing outputs at key checkpoints.
5. Test Benches in HDL Verification : Test benches are used to automate stimulus generation and output checking. Verification can be done cycle-by-cycle for detailed checking. Increasingly, real-time or near real- time FPGA emulation is used. It allows testing in the actual system environment. Essential for complex chips and real-world interactions (e.g., wireless LAN chips). Helps model unpredictable effects like interference.
6. Simulation at Various Levels of the Design Hierarchy :
Functional equivalence can be verified at multiple levels. RTLlevel allows system-level behavior testing. Gate-level and transistor-level testing is more challenging due to long simulation times. Hierarchical verification starts with small modules and verify them separately. Use modular interfaces to ensure system-level functionality. A well-structured verification hierarchy increase the chance of first-time functional success.
7. Best Practices for Functional Testing : Simulate real-world usage as closely as possible. Move up the simulation hierarchy as modules are verified. Replace lower/gate-level models with higher-level functional models when verified. Surround top-level models with a real-world software env. for testing. If time permits, functional tests should be applied at all levels, including gate and transistor levels.
8. Advantages of FPGA-Based Emulation Over Simulation : Faster execution, often near real-time. Allows interfacing withactual analog signals. Provides finer observation and monitoring compared to final chip implementation.
Post-Fabrication Testing & Debugging :
When a chip returns from fabrication, initial tests are conducted in a lab environment.
Test Setup Requirement : A circuit board with, variable VDD with power measurement , signal connections such as analog/digital I/O as needed, stable variable-frequency clock, serial, parallel, or PCI for data exchange.
Software and Debugging : Develop software to interface with the chip via UART, serial, or bus. Essential functions include register read/write. Logic analyzer connections can also aid in debugging.
Initial Tests :
1. Smoke Test: Gradually increase VDD while monitoring current. Static circuits should show no current; analog circuits will show quiescent current.
2. Clock and Register Check: Enable the clock at a reduced speed and verify register integrity using PC-based software.
3. Logic Analyzer Tests: Download test patterns from the verification test bench.
If a chip has a BIST, commercial software or manual bottom-up approach is used for automated validation.
Debugging Strategies:
- Keep a logbook of all tests.
- Change one variable at a time and document results.
Once functionality is confirmed, evaluate performance metrics like power, speed, and analog characteristics. Store test results digitally for documentation and collaboration.
Common Chip Issues & Fixes :
1. Slower than expected: Reduce clock speed /increase VDD.
2. Race conditions: Apply heat to identify temperature sensitivity.
For analog circuits, factors like noise and process variations may impact performance. However, systematic debugging remains the key to resolving issues efficiently.
Manufacturing Tests:
Manufacturing tests ensure that every gate functions correctly, addressing potential defects that may arise during chip fabrication or accelerated life testing (stress testing under high voltage and temperature conditions).
Common Defects:
- Layer-to-layer shorts (e.g., metal-to-metal)
- Discontinuous wires (e.g., due to vertical topology)
- Missing/damaged vias
- Gate oxide shorts to substrate/well
Resulting Circuit Faults :
- Nodes shorted to power or ground
- Nodes shorted to each other
- Floating inputs / Disconnected outputs
Testing Strategy : Confirm gate/register functionality and detect manufacturing faults
1. Wafer-level Testing: Early detection to avoid packaging bad dies
2. Post-Packaging Testing: Cost-effective if yield is high and packaging is cheap
Test Strategy Based on Economics :
- High Yield + Low-Cost Package (e.g., plastic): → Test after packaging
- Low Yield + High-Cost Package (e.g., ceramic): → Test at wafer level to reduce waste
Efficiency Enhancements : Use on-chip test structures for full-speed wafer testing, Minimizes required pin connections and reduces fixture cost
Test Assumption : Assumes chip functionality is correct , Focuses on exercising all gate inputs and observing all outputs.
Testing of a Chip:
Tester & Test Fixtures :
What is a Tester :
A tester applies a sequence of electrical stimuli to a chip or system under test (SUT). Monitors and records the results to detect faults. Available in various forms depending on the test environment and chip type.
Types of Test Fixtures:
1. Probe Card – For wafer-level or bare-die testing
2. Load Board – For packaged chip testing
3. Bench PCB – For manual/automated lab testing
4. In-System PCB – Tests chip in its real-world application context
Production testers :
- These are are high-end, general-purpose systems used for chip testing. They feature configurable I/O ports(drive current, voltage levels) and large RAM per pin. Inputs are driven and outputs
- These testers are expensive and essential for high-precision with high-throughput production testing, high-end configurable systems with cycle-by-cycle control , ability of driving input/output pins with precise voltage, timing and equipped with test memory, advanced diagnostic capabilities
Test setup :
Drive-electronics Cabinet , Controlling Workstation , Test Head (where the DUT is placed via a load board)
Production Testing & Cost Considerations:
Test Execution Process:
Test program compiled and downloaded into the tester DUT (chip) placed on probe card/load board Inputs applied, outputs sampled, results compared Faulty chips marked (e.g., ink dot) and sorted. Automated handling repeats the cycle efficiently
Advanced Testing – Shmoo Plots :
Vary voltage (e.g., 3V–6V on a 5V part) and timing. Reveal chip performance sensitivity across conditions Useful for analyzing setup/hold time margins and voltage tolerance
Cost & Efficiency Factors:
- High-frequency or analog/RF testing is expensive
- Time-based billing: shorter tests = lower costs
- Trade-off between test coverage and cost
- Lab testers offer a low-cost alternative with reduced
capabilities
Test Program :
The tester operates based on a test program, typically written in a high-level language tailored to the tester (e.g., with built-in primitives). This program defines input patterns and expected output assertions. If the observed outputs deviate from the expected values at the specified times, the tester flags an error. Before running the tests, the program configures essential tester attributes, including:
- Setting supply voltages
- Mapping signal names to physical tester pins
- Defining pin directions (input/output) and VOH/VIH levels
- Configuring the tester clock
- Establishing pattern and assertion timing
For each chip tested, following steps are performed:
- Apply supply voltages
- Send digital stimuli and capture responses
- Compare responses to expected value
- Log and report any discrepancies
Silicon Debugging & Silicon Failure :
Silicon Debugging : Challenging when a root cause of chip malfunctions is unclear from pin/scan chain measurements.
Several techniques enable direct access to the silicon:
1. Probe Points: Small metal pads (5–10 µm) on the chip surface allow direct probing of key circuit nodes using fine-tipped probes under a microscope.
2. Electron Beam & Laser Voltage Probing: E-beam probes use scanning electron microscopes to measure on-chip voltages, while Laser Voltage Probing analyzes modulated light reflections to deduce switching wave forms. Picosecond Imaging Circuit Analysis captures light emissions from switching transistors.
3. Infrared Imaging & Liquid Crystal Techniques: IR imaging helps detect "hot spots" caused by resistive shorts, while liquid crystal coatings can reveal temperature variations.
4. Focused Ion Beam (FIB) & Laser Cutting: FIB can modify circuit connections by cutting or depositing metal, offering faster debugging than mask changes.
Silicon Failure :
Silicon failures fall into three categories:
1. Manufacturing failures stem from defects or parametric deviations. Debugging can help reject bad chips or refine designs for better yield.
2. Functional failures arise from logic bugs or physical design flaws, typically fixed by improving verification.
3. Electrical failures occur when a logically correct chip malfunctions under specific conditions like voltage, temperature, or frequency.
Shmoo Plot :
Shmoo plots aid in debugging electrical failures by mapping test results across voltage and frequency ranges. A well functioning chip should operate at higher speeds as voltage increases. Variations in shmoo patterns can reveal underlying issues such as charge sharing, race conditions, leakage problems, and coupling noise. Temperature based shmoo plots can also highlight failure modes.
Design for Manufacturability :
Circuits can be optimized for manufacturability to increase their yield. This can be done in a number of different ways.
1. Physical Design Optimization :
Increase wire spacing to reduce short-circuit risks , Enhance layer overlap around contacts/vias to minimize misalignment issues , Use multiple vias at intersections to prevent open circuits, Modern EDA tools increasingly automate these improvements.
2. Redundancy :
Include spare memory rows/banks to replace defective units. Laser-cut fuses or programmable fuses enable reconfiguration post-test . Faulty memory banks can be disabled via software
3. Power Management :
High power can lead to metal migration and thermal degradation. Use of low-power design techniques, efficient packaging, and heat sinks to manage thermal load
4. Process Variation Handling:
Simulate across process corners. Use Monte Carlo analysis to account for statistical process spread and optimize design centering
5. Yield Analysis:
Analyze failed dies to identify recurring structural issues, Redesign critical layout areas (e.g., wider polysilicon or metal strapping) to improve yield.
How do you blend AI-driven innovation, open-source collaboration, and a global perspective to transform semiconductor verification? In this episode of The Semiconductor Podcast (TSP), we sit down with Srinivasan Venkataramanan, CEO of AsFigo, to unpack his journey and vision for the future of VLSI.
Here’s what we have discussed :
🛤️ From IIT Delhi to AsFigo—a career built on passion for VLSI and verification excellence
🌍 Open source as the catalyst for academia–industry collaboration
🤖 How AI is reshaping EDA and redefining verification methodologies
📚 The story behind the SystemVerilog Assertions Handbook & why his books matter for engineers and educators
🔍 Biggest verification challenges today—and how AsFigo is solving them
🇮🇳 India’s semiconductor evolution, startup culture, and real-world hurdles
🎤 Memorable moments from DVCon, SNUG, and DesignCon, plus advice for aspiring verification engineers
If you’re passionate about chips, code, and the future of the semiconductor ecosystem—this episode is a must-listen.
In this podcast series, discussion on VLSI and its related fields is presented, focusing on recent developments and advancements in the industry. Topics such as the latest trends and innovations in semiconductor technology are explored, offering insights into the evolving landscape. Career guidance is shared, providing practical advice for navigating the field, along with success stories that highlight the journeys of professionals who have made their mark in VLSI. Whether for students, professionals, or those interested in the subject, valuable knowledge is offered to help stay informed and succeed in this dynamic area.
Guest : Srinivasan Venkataramanan
Srinivasan Venkataramanan is the Chief Executive Officer of AsFigo, a London-based company advancing semiconductor design and verification solutions. With over two decades of experience in EDA, semiconductors, hardware verification, and AI-driven design, he is recognized globally as a technologist, entrepreneur, and thought leader in the VLSI ecosystem. He is also the CEO & Co-Founder of VerifWorks and CTO at CVC Pvt. Ltd., driving advanced verification solutions and talent development in India. His career spans leadership roles at Synopsys, Intel, Philips/NXP, Real Chip Communications, and Breker Verification Systems, working on cutting-edge ASIC and SoC verification technologies. Srinivasan contributes actively to the global semiconductor community as a Technical Program Committee (TPC) member for DAC, DVCon US, DVCon India, and DVCon China, and serves on the Advisory Board of Blue Horizons. He has also focused on Machine Learning for chip design as Principal Engineer at Synopsys Inc. A strong advocate of industry standards, he served as Vice Chair of the IEEE 1647 E Language Working Group and Coordinator for IEEE-SA India in VLSI & EDA, and was instrumental in bringing DVCon to India. He holds a Master’s degree from IIT Delhi and is known for pioneering verification methodologies, authoring technical papers, and mentoring engineers worldwide.
💡 Subscribe to The Semiconductor Podcast for more expert insights and discussions about the ever-evolving semiconductor industry!
Credits :
Image by Lucas Wendt from Pixabay
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CMOS technology is the backbone of modern electronic devices, powering everything from smartphones to microprocessors. Defects and failures in CMOS ICs can significantly impact performance, yield, and overall reliability, making it critical to understand their causes and effects. This presentation will cover the bridging defects,gate oxide short, open circuit defects. We will explore the causes of defects and failures in CMOS ICs, detection techniques, and strategies for preventing and mitigating these issues to improve yield and reliability. Effective defect management is crucial to optimizing semiconductor manufacturing processes and is essential for sustaining Moore's Law as process nodes continue to scale down.
Bridging Defects:Unintended connections between circuit parts causing shorts, leading to malfunctions. Caused by process variations in fabrication.
Gate Oxide Shorts: Breakdown of the gate oxide layer creating conductive paths, impairing transistor performance. Result from deposition or etching defects.
Open Circuit Defects: Breaks in conductive paths preventing current flow, causing non-functionality or failure. Caused by poor bonding or material defects.
These defects degrade performance, reduce yield, and increase production costs. Detected via advanced testing like electrical and thermal imaging; minimized through improved process control and inspection. Unresolved defects harm device reliability, emphasizing the need for improved fabrication techniques.
Bridging Defects in ICs:
Unintentional connection between two or more circuit nodes. Causes abnormal electrical behavior based on circuit parameters & topology .
Major Bridge Defect Variables :
1. Type: Ohmic or nonlinear
2. Location: Intragate i.e within transistor internal nodes , across I/O nodes of separate logic gates, Power rail to ground rail
3. Circuit Topology: Combinational or sequential
4. Interconnect Materials: Metal, polysilicon, diffusion region
2. Large material deposits shorting multiple interconnects
3. Gate oxide shorts:
4. Ruptures in transistor thin oxide
5. Connect gate to silicon structures
Impact on ICs :
1. Memory cells & flip-flops: May behave differently from combinational circuits
2. Power rail shorts (VDD to GND): Do not affect signal paths but must be controlled , lead to power leakage, reducing product lifespan , critical for low-power & battery-operated devices.
Critical Resistance in Bridging Defects :
What is Critical Resistance ?
Critical resistance is the defect resistance above which the circuit functions correctly. Determines the impact of a bridging defect on circuit behavior.
Lower resistance → Higher risk of functional failure.
Defect Activation: If no voltage drop across the bridge → No current → Defect is inactive.
If current flows through the bridge → Voltage drop → Defect is activated.
Voltage & Current Response to Defect Resistance:
Higher resistance → Output voltage approaches fault-
Threshold for Logic Error: If defect resistance is ≤ 5 kΩ, logic error occurs. If defect resistance is > 5 kΩ, logic is correct but may be weak & noise-sensitive.
Factors Affecting Critical Resistance :
Transistor Strength i.e, W/L Ratio determines driving capability against defect. Logic Threshold Voltage (VTL) defines functional failure threshold. Found at Vin = Vout on the transfer curve (~VDD/2). Critical resistance depends on circuit design & defect location. Functional failure occurs when the defect overpowers transistor drive strength. Higher resistance = More tolerable defect; lower resistance leads to logic errors & noise vulnerability.
Fault Models for Bridging Defects :
Bridge defects cause intermediate voltages at shorted nodes. Analog simulators (e.g., SPICE) can accurately analyze: (1) Operation regions of affected transistors , (2) Intermediate voltages at short nodes, (3) Induced power supply current increase
Test & diagnosis goal :
1. Predict faulty behavior and generate test vectors to expose bridging faults.
2. Most test pattern generators use a logic-level netlist to derive test vectors.
3. Logic simulators fail to model BFs accurately due to non-standard logic voltages.
4. Analog simulation is too slow for large circuits and often unnecessary.
5. Logic fault models bridge the gap between analog behavior and logic-level representation.
6. These models provide a practical way to simulate and detect BFs during testing.
Common logic-level bridging fault models :
1. Stuck-at
2. Pseudo stuck-at
3. Logic-wired AND/OR
4. Voting
5. Biased voting
Logic Fault Models:
1. Stuck-at Fault Model (SAF) :
Simplest and most widely used logic fault model. Originated during the bipolar transistor IC era . Accurate for that technology. Proven inadequate for CMOS, but still dominant due to computational efficiency, industry acceptance and established tools. A fault model where a signal line is permanently stuck at logic ‘0’ (stuck-at-0) or logic ‘1’ (stuck-at-1), regardless of actual circuit behavior.
2. Pseudo Stuck-at Fault Model :
This model leverages leakage current behavior from bridging faults. Simplifies ATPG and improves fault coverage. Defect detection is confirmed when the fault effect reaches the gate output. Detection doesn’t require propagation to primary outputs. Fault effects observed via quiescent current at the power supply pin. Minimal changes needed to adapt existing stuck-at ATPG tools.
3. Logic-Wired AND/OR Model :
Logic-wired fault models for bridging faults were originally developed for bipolar technologies like ECL and TTL. In these technologies, if two logic gate outputs are accidentally connected/shorted, the result often behaves like a logic OR or AND gate. This is because one logic level is electrically stronger than the other, so when a short occurs, the stronger signal dominates. This logic fault model is more versatile than the stuck-at model. Although this model doesn't work well for CMOS technology, where neither logic level is inherently stronger. In CMOS, the voltage at a shorted node depends on several factors, including the relative sizes of the gates, the resistance of the short/bridge, and the input values.
4. Voting Model :
The voting model improved the way bridging fault are represented . It considers what happens when shorted nodes are forced to opposite logic levels—pMOS and nMOS transistors compete to control the output. The model assumes that the group of transistors with the strongest drive or higher current will determine the final logic value. The voting model doesn't consider the effects of nonzero resistance in the bridge or the logic threshold of the connected gates. If the bridging resistance isn’t zero, the outputs of the shorted gates can sit at different voltages due to voltage drops, which might be interpreted as different logic levels by following gates.
5. Biased Voting : This model solves the problems faced by circuits with logic gates that have different threshold voltages. Unlike the voting model, which uses a fixed starting voltage to calculate transistor conductance, the biased voting model calculates conductance based on the actual voltage at the bridged node. This way, it better reflects the real, nonlinear behavior of transistors when determining a device’s driving strength. It also considers the varying threshold voltages of the logic gates connected to the shortened outputs.
6. Mixed Description : A bridge defect causes analog behavior in the circuit, it requires a mixed modeling approach for accurate analysis. In this method, the entire circuit is modeled using digital logic, except for the fault location, which is simulated using an analog tool. This approach combines the accuracy of analog simulation at the defect site with the speed and efficiency of logic-based simulation for the rest of the circuit.
Feedback and Non Feedback Bridging Faults:
At the circuit level, we talk about two types of bridging faults (BFs): intragate and intergate.
Intragate BF : Unwanted connection/short between parts inside a single logic gate.
Intergate BF : Unwanted connection/short between two or more different logic gates.
This difference is important for ATPG tools, because the way the circuit is described (either using gates or transistors) affects which faults the tools look for. In combinational circuits, there are two types of bridging faults:
1. Non-feedback bridging faults,
2. Feedback bridging faults.
Non-feedback bridging fault :
A non-feedback bridging fault is a short or unwanted connection that doesn’t create a loop or path from a gate’s output back to any of its inputs. This type of fault is the most basic kind of bridging fault. When this kind of defect is triggered, the shorted nodes may settle at a voltage level between 0 and 1 — not fully high or low — depending on the resistance of the short and the threshold voltage of the gates that receive the signal.
Feedback bridging fault :
Feedback bridging fault happens when a short/unwanted connection creates a situation where the output of one gate can affect its own input — through a logic path. In other words, it forms a loop. Depending on how the shorted gates are connected, three situations can occur when an input is applied to
the circuit:
1. Case A: The value at node j does not depend on node i → this behaves like a non-feedback bridging fault.
2. Case B: The value at node j is the same as at node i → this is called a non-inverted feedback bridging fault.
3. Case C: The value at node j is the opposite of node i → this is called an inverted feedback bridging fault.
Bridging Faults in Sequential Circuit :
Control Loops in Sequential Circuits :
- Floating state: Memory state not controlled by logic
- Forced state: Memory state driven by preceding logic
- Detection depends on circuit design and location of defect
BFs in Flip-Flops :
Behavior depends on flip-flop design (CMOS vs. NAND-based) . Some BFs do not elevate current but affect timing (setup/hold time).. Design modifications can improve current-based detectability
BFs in Semiconductor Memories:
BFs in SRAMs may not always elevate quiescent current. Floating control loops can prevent detectio. BFs in DRAMs cause logic errors but do not elevate current
Bridging Faults & Technology Scaling :
Physical defect mechanisms remain unchanged.Impact on IC behavior changes due to scaling effects.
Key scaling effects:
Critical resistance decreases → Makes logic testing less effective. Higher leakage currents → Reduces effectiveness of traditional quiescent current testing. Advanced detection needed → Delay-based or leakage variation monitoring
Gate Oxide Short :
1. Introduction & Model :
GOS have been a persistent issue in MOS technology since 60s. Occur due to rupture in SiO₂ layer between polysilicon gate and Si. Thin oxide layer is critical for controlling charge flow in the channel. Undamaged oxide regions may still function, allowing charge inversion. In some cases, transistors with GOS may remain functional exhibiting degraded drain current. The electrical behavior differs based on the type of gate oxide short.Two types of GOS : (1) Thermal filament growth at gate edge due to high over voltage and strong electric-field, causing breakdown and filament formation between gate and source. (2) Particle-induced short between gate and p-well, caused by contamination.
3. Gate Oxide Short Models :
Figure illustrates an inverter cross-section in n-well CMOS technology. Gate-drain/Gate-source oxide shorts are modeled based on the doping types of the connected terminals. Six distinct parasitic connections can occur if gate material merges with substrate. GOS connects gate polysilicon to the drain, source, or bulk of the transistor.
The electrical model depends on doping polarity:
(1) Same doping type → modeled as a resistor.
(2) Opposite doping type → modeled as a pn junction diode.
Electrical behavior of each shorted path varies with the type of contact formed. Detailed modeling helps in accurate fault analysis and reliable simulation.
Sometimes, a direct (Ohmic) connection forms between the gate and the drain or source in an nMOS transistor. This happens when the thin oxide layer breaks between the n- doped polysilicon gate and the n-doped source or drain. It's similar to placing a resistor between the gate and the source or drain.
2. nMOS Transistor Gate–Substrate Oxide Shorts :
Ohmic connection forms when an oxide rupture links n- doped polysilicon gate to n-doped drain or source in an nMOS transistor. Electrically similar to an external resistor connected between gate and drain/source terminals. These shorts can result from: weak oxide layers, high electric fields at gate edges (more prone to breakdown than gate center)
When a pMOS transistor gate gets shorted, it can form a diode if the short connects an n-doped polysilicon gate to a p-type source or drain. If this diode-like short happens at the source, it limits the gate voltage. If the short is to the drain, things are more complex—the diode acts like a nonlinear feedback loop from the output/drain back to the input/gate. But if the gate is made from p-doped polysilicon and shorted to the source or drain, it creates a direct conductive/Ohmic short, not a diode.
2. pMOS Transistor Gate–Substrate Oxide Shorts :
If a defect occurs between the n-doped polysilicon gate and the substrate of a pMOS transistor, it creates a low-resistance (Ohmic) connection to the substrate, since both have the same doping type. When power is applied, this defect combines with the transistor to create a parasitic pnp bipolar transistor.This effect becomes more serious in single-well CMOS structures, where: The parasitic bipolar transistor (caused by the defect) can interact with other parasitic devices in the circuit. This can trigger latchup, a condition where the circuit enters a high-current, unstable state (with a negative slope in the I-V curve), potentially damaging the device.
Open Circuit Defects :
Open circuit defects in ICs are unintended breaks in metal/polysilicon/diffusion interconnects, leading to diverse failures. Unlike bridge defects, they are more complex and harder to detect, often causing partial or intermittent issues. As CMOS scaling pushes metal lines below 130 nm and increases via height-to-width ratios, the risk of open defects rises due to billions of vias and extensive interconnects in modern ICs.
Challenges in Detecting & Testing Open Defects :
These are breaks or partial discontinuities in conductive paths (like wires or vias) that interrupt current flow. Partial opens can cause intermittent faults, making detection and localization difficult. Standard models like stuck-at or bridging faults often miss open defects, especially partial or resistive ones. Advanced models (IDDQ, transistor-level, resistive-open) are more effective but require more resources and time. Open defects may not be active under normal conditions. They often manifest only under specific voltage, temperature, or timing stress, leading to unpredictable behavior. As feature sizes shrink (e.g., 5nm, 3nm), narrower wires and vias increase the likelihood of open defects. Process variations can either hide or worsen these defects depending on design tolerances. Opens may escape detection during factory testing but fail during actual use (latent defects). This poses serious risks for high-reliability sectors like automotive, medical, and aerospace.
Modeling Floating Nodes :
1. Capacitor Coupling in Open Circuits :
When an open defect occurs in a metal line, the floating node behaves like a capacitor. Depending on how the broken metal line is positioned over the IC substrate (GND) and the well area (VDD), the node experiences capacitive coupling. This coupling can create a capacitor voltage divider, affecting the floating node’s voltage.
2. Influence of Surrounding Lines :
In modern ICs, metal lines are closely packed, and adjacent lines create parasitic capacitance. If an open defect occurs in one line, the floating node’s voltage is significantly influenced by adjacent active lines.
3. MOSFET Charge Influence :
If the floating node is connected to a MOSFET gate, the charge stored at the transistor gate and the voltage at the transistor drain play a crucial role in determining the final gate voltage. This could lead to unpredictable logic states.
4. Tunneling Effects :
For very small open defects (narrow cracks in metal), quantum mechanical electron tunneling can occur, allowing some current to pass through the defect. This can create an unusual failure mechanism where a gate functions at low frequencies but fails at higher frequencies.
Classification of Open Defects :
Open defects can manifest in different ways, impacting circuit functionality in various degrees. Based on failure analysis, these defects are categorized into six broad classes:
1. Transistor-On Open Defect : Affects a single transistor gate.The floating gate voltage is influenced by parasitic capacitive coupling. The transistor may still function, but with a shifted threshold and increased power consumption.
2. Transistor Pair-On Defect : Occurs when an open defect affects both the PMOS and NMOS transistors of a logic gate. The floating node may settle to an intermediate voltage, causing both transistors to conduct simultaneously, leading to increased static power dissipation.
3. Transistor Pair On/Off Defect : If the floating node voltage is near VDD or GND, one transistor remains permanently ON while the other is OFF. This can cause a stuck-at logic error, where the output is permanently HIGH or LOW.
4. The Open Delay Defect : In cases where electron tunneling is the only conduction mechanism across an open, the circuit may function at low frequencies but fail at high frequencies. These defects become particularly noticeable in high-speed digital ckt.
5. Memory (Stuck-Open) Defect : A transistor remains OFF due to an open, but previous charge stored in the circuit keeps it functioning correctly. The defect manifests only when certain input sequences cause the stored charge to be lost.This is one of the most difficult defects to detect using standard functional testing.
6. Sequential Open Defects : Occur in sequential logic circuits, such as flip-flops and latches. Can lead to logic race conditions, erroneous clocked behavior, or timing violations. These defects may or may not elevate static power consumption.
