One question we frequently face whether one can change domain from embedded systems to VLSI. Now lets find answer to it.
VLSI is the domain where a chip is designed on physical Silicon. Fabricating a chip starting from a spec is the core of VLSI. Whereas Embedded systems is duo of computer hardware and software designed for specific functions for the larger systems.
So if you are working in Embedded Systems domain and have few years of industry experience . Leveraging that experience in VLSI domain is not possible. Moreover once you have 3-4 years of experience you have reached a point where you will get attractive salary, you have developed a good understanding of the industry and by now your networking also grown for good.
Even after all these, if you are really interested to change the domain first read about it. There are so much free material available in internet. Read them.
We have different in-depth series in TechSimplified Tv and articles on this blog. Watch them or read them, you will have fair idea about the domain. In addition to that you can go for paid course where you will get a certificate at completion. That certificate will help you. If you are determined enough, go ahead and start your journey. A person who has worked in embedded systems with good programming skill can find some scope in RnD teams of EDA companies. For example RnD teams of EDA companies require people from computer science/ strong programming background. In many IP companies , CAD platform is designed by C and TCL. A person with strong programming skill in these languages might get a chance to work. Moreover System team, Shipping and Delivery team require people with strong programming skill. If you are working in embedded systems background for quite some time and want to join VLSI/Semiconductor industry then first thing you must do is that, try to understand where you stand with your skill set with respect to required skill set. That you can do by keeping a close eye on published job openings in different job portal or professional networking site. Try to understand the JD to find out which kind of skill set is required. If you have those skill set then congrats, half of the work is done. If you lag in skill set, don't get upset,make a plan to acquire those skill set. For domain knowledge of front end or back end or to know about the basics of different steps of VLSI flow you may join some finishing school and after completion of the course you will get a certificate. Try to gather some domain knowledge. You might aim to join any RnD team of an EDA company where you will contribute to develop an EDA tool. A little bit generic knowledge on how that tool will impact a customers work or where actually in the VLSI flow it is used will help you during the interview. Now once your preparation part is done, rewrite your resume and upload to multiple job portals. Also search for jobs on professional networking sites and apply. Although we would recommend don't plan such change if it is not absolutely necessary.
Want to know about Scope and Future Trend in Embedded Systems, read here.
In this article we will discuss about ground bounce and its effect on circuit performance.
Power supply noise and ground bounce can cause considerable path delay variations in VLSI Circuit. In any VLSI circuit Source and Ground are two power lines are present and noise in any of them will cause considerable delay in performance. Ground Bouncing noise is the primary cause of false switching in high speed circuits and a major cause of poor signal quality. Within a circuit multiple blocks are there and not all of them are in similar logic state all the time. Let's take an example where two adjacent block are there and one of them are in sleeping state or in between a transition. Since the ground and power lines are shared , during wake up event the bouncing noise generated in one power domain is transferred to the other block and can flip the logic states of the block. This noise is known as Ground Bounce Noise.
A major component of the circuit noise is the inductive noise. It is a critical and challenging design task to control the amount of inductive noise that is inserted into the power planes. Package pins, bonding wires, and on-chip IC interconnects all have parasitic inductance. When an inductor current experiences time-domain variation, a voltage fluctuation is generated across the inductor. This voltage is proportional to the inductance of the chip-package interface and the rate of change of the current.As a result, when the logic cells in a circuit are switched on and off, the voltage levels at the power distribution lines of the circuit fluctuate. This inductive noise is sometimes referred to as the simultaneous switching noise because it is most pronounced when a large number of I/O drivers switch simultaneously.
Correlation of Power and Ground Bounce
Ground Bounce in Ground Noise. Power Bounce is Noise Glitch on Power Line. When Ground Bounce and Power Bounce are in Phase (Common Mode Noise) they will not effect the local logical cells but will degrade the signaling between two distant cells. Within a chip the metal connection runs for meters and meters if we sum them up. SO if we measure signal level in any two distant cell we might find variation in ground and power due to noise we discussed. When Ground Bounce and Power Bounce are out of phase (Differential Mode Noise), they adversely effect the local logical cells causing jitters in timing circuits.
Ground Bounce Mitigation Technique :
Many design techniques have been used to reduce the effect of ground bounce, such as :
i. Power Gating Technique
ii. Stacking Power Gating Technique.
iii. Various Multi Threshhold CMOS(MTCMOS) Technique.
iv. Adding Decoupling Capacitors (DECAP)
v. Having separate ground buses for I/O buffers and internal circuitry.
vi. Widening Ground Interconnect Buses
vii. Evenly distributing circuitry among many Power and Ground pins.
Embedded means something that is attached to another thing. An embedded system can be thought of as a computer hardware system having software embedded in it. An embedded system is a microprocessor- or micro controller-based system of hardware and software.
It is designed to perform dedicated functions within a larger mechanical or electrical system. Such a system can be small and independent or large and computational.
At core an embedded system consists of 3 things:
An input Device which collects input from user or environment via a sensor or a remote control. A Micro-controller i.e the the Brain or the processing unit. It instruct the output device to perform as per the logic defined inside the collected information from input device.
An output devics which take instruction from micro-controller and perform accordingly.
Microwave, TV, Calculator, Audio Player, Digital Camera, Printer, Traffic Lights, Digital Thermometer, Set Top Box (TV), Wifi Router, Modem are some popular consumer electronics products we use da to day basis and all of them are example of embedded systems.
Embedded system is a vast domain. There are huge number of products which are field specific like products used in medical electronics sector, aerospace, automobiles, defense, toys, consumer electronics, food industry, telecommunication, Industrial machines, space, agriculture, construction all of them are example of embedded systems.
So obviously mentioned fields has huge scope of employment. All the leading brand in consumer electronics, medical equipment, automotive industry can offer employment in embedded systems.
Required Skill :
Now let's see what are the skill required for such jobs.
1. Programming Skill : Earlier Embedded System was mostly hardware a little software but now the scenario is exactly opposite. The most important programming language required is C. Basic to moderate knowledge of C++, LabView, Python, Rust and Assembly Language can also be helpful.
Working knowledge of interfacing micro-controllers with different sensors and peripherals, Kernel Programming, Device Drivers, Real Time Operating Systems (RTOS) are also helpful.
2. Circuit designing skills : Understanding of circuits, Printed Circuit Boards,Power Supply Circuit Designing, sensors, microprocessors, memory, CAD and other subjects can be useful for systems engineers.
3. Analytical skills : Systems engineers usually works with large volumes of product data and information to design effective solutions. Knowing basic analytical models and tools can be beneficial for systems embedded engineers.
4. Communication skills : Embedded systems engineers coordinate with several experts from the production, hardware, software, management and product design departments. Collaborating with other engineers to exchange feedback and work as a team is essential for systems engineers. They may also have to maintain meticulous records and documentation of their process, which requires strong written communication skills.
5. Attention to detail : Designing software systems for embedded devices is a complex process and requires focus and attention to small details.
Some other skills are very basic and essential for accomplishing work responsibility on day to day basis, such as
6. Self Learning Ability : Electronics is a market driven subject and self learning ability will help someone to upgrade with time.
7. Interest in Learning new hardware
8. Patience to Read Datasheets
9. Documentation as per company norms
10. Following Software Development Life Cycle or SDLC
11. Working in a Team
12. Completing Work in Deadlines
13. Making Reports as per the Company Requirement
Popular Job Role :
We have listed some popular job role in embedded systems domain :
1. Biomedical Engineer : Responsible for
i. Design, development, safety testing, repair and maintenance of biomedical equipment
ii. Ensures the equipment is working with proper functionality and quality control standards.
Requires a bachelor’s degree and 0-2 years of direct experience in the field.
2. Embedded Systems Architect : Responsible for
i. designing and implementing software of embedded devices and systems
ii. review and design code
iii. integrate and validate new product designs
iv. develop system software
Proven work experience in software engineering required.
3. Embedded Software Engineer : Responsible for
i. development of embedded software programs.
ii. required to collaborate and work according to client specifications and needs.
iii. client-facing communication skills are necessary.
iv. often needs to work as part of a larger team.
Specialized degree in embedded software engineering is needed.
4. Embedded Systems Engineer : Responsible for
i. design, development, production, testing, and maintenance of embedded systems
ii. run regular tests to eliminate potential issues, provides system level support working with cross functional teams ( Mechanical, Software , Hardware, etc) .
Systems Engineer provides Subject Matter Expert level experience in Software & Hardware Integration. Computer science or engineering degree required.
5. Firmware Engineer : Responsible for
i. creating software used in programmable devices.
ii. designs and implements algorithms for firmware and create technical documents for firmware usage.
iii.oversees firmware development process from design to creation.
iv. manages updates and provides support.
May be asked to alter existing software based on company needs. Firmware engineering certification required.
6. Hardware Engineer : Responsible for
i. all aspects of the electrical system design which includes high-speed digital, power management, PCB layouts and thermal management.
ii. collaborates with algorithm and software team.
iii. works directly with System Architecture, Firmware, Mechanical and Electrical Engineers.
Requires a bachelor’s degree in a related field.
7. Hardware Test Engineer : Responsible for
i. design, implementation and testing of hardware systems
ii. must work autonomously and have strong problem solving skill
A bachelor's degree in computer science or a related field is mandatory.
8. Mobile App Developer : Responsible for
i. writing software for hardware functionality on various handheld mobile devices
ii. work closely with design and development teams.
Bachelor’s degree and extensive software development experience required.
9. Printed Circuit Board Designer : Responsible for
i. designs and development of circuit boards
ii. works with larger team. Typically works for software companies
iii. must have team collaboration skills and be able to work independently
Background in software engineering or multiple years of experience designing circuit boards is required.
10. R&D Engineer : Responsible for
i. researching and creating new products and test existing products.
ii. often works with marketing teams, executive teams, and other related teams.
R&D engineers report to project managers. Must have good leadership and communication skills. An engineering background is preferred.
11. Software Test Engineer : Responsible for
i. developing and implementing testing methods
ii. reporting test results and recommending improvements to software programs
iii. creates Test software to test functionality of Product Code.
Job requirements typically includes a bachelor’s degree along with excellent technical skills, communications skill and creativity.
Like any domain initial packages are not very high, although experience of 3-4 years, you will get attractive packages. And experienced embedded system developers have extremely high demand in India.
Is Embedded Systems a Good Career Option ?
Yes obviously. For those who has inclination and basic subjective degree like ECE, its a great match for them.
To accelerate your preparation you can join online courses.
Future Scope in Embedded Systems:
Online viewing is increasing and accordingly the use of the embedded system and IoT is growing rapidly.
1. Engineer in embedded Linux : Responsible for i.developing low-level components along with significant embedded limitations
ii.running the unit tests on them
2. Embedded IoT application developer : Responsibility includes
i. design and develop embedded software in C and C++ for various apps
ii.compliance checking of new product solution
3. Cyber-security embedded developer : Responsibility includes
i. designing APIs to keep user data safe
ii. understanding hardware security modules, public key infrastructure transport layer security, and typical application security flaws,
iii.testing and troubleshooting.
4. Embedded application engineer : Responsibility includes
i. managing the frameworks for embedded software
ii. working in open source stacks and apps
iii. enhancing skills in various programming languages, consisting of Embedded C and Python
5. Engineer of micro-controller firmware : Responsibility includes
i. writing firmware for micro-controllers
ii. using C and C++ for designing and developing embedded software
How to enter the domain :
In a nutshell getting a job require few factors at the right place like demand in the company and supply of eligible fresher.First entering any field identify your interests and then get the right kind of education. If possible enroll for courses in relative domain. Apply your knowledge to find internship. Write your resume and apply for the job. Always keep yourself updated with latest trend in technology.
Want to know whether domain shift from Embedded systems to VLSI is possible or not , read here.
In this article we will discuss about Design Rule Check and its importance in VLSI.
Design Rule and Design Rule Check :
Design Rule are set of rules which a designer must follow to create the layout in GDS/ GDSII format so that the design is eligible for manufactured in intended technology. All the rules comes from foundry and written in Design rule manual or DRM.
Design Rule Checking or DRC verifies whether an IC has been designed by following constraints imposed by the process technology to beused for its manufacturing. In short DRC is the process to confirm that design rules have been followed while designing the circuit. DRC checking is an important part of the physical design flow. It ensures that the design will not result in a chip failure.
Design Rules specify a minimum feature size or spacing requirements or some geometric constraints between layers/masks of the same type or between different types.Design Rules are mentioned in ASCII/PDF Format in the Design Rule Manual/Document. Each Physical Verification Tool have its own format of reading the Design Rule.It means design rule files for one tool cannot be used for a second tool. Second tool from another EDA vendor require different set of files. However, fundamentally the rules are same in both set of files. Design Rules Set are usually supplied by foundry and comes along with the PDK/DK distribution. Technically the Design Rules are the interface between design-engineer from SOC design house and Process Engineer from foundry. Rules are written in a way that they can be forward compatible to upcoming generations. Design Rules ensure that design made through EDA-Software will perform as expected and with proper functionality after fabrication.
The whole VLSI design flow is divided into front end and back end. Design rule check is done in back end part.
Back-End in Analog and SOC Design Flow:
Lets discuss the steps involved in analog and digital design.
In Analog design PD starts after Schematic-Design which is done in front end. Then comes layout. There are several variation in custom and semi-custom layout. Once the layout is done DRC and LVS check are done on that layout.If any error found in these steps we might need to go back to layout step. Once the DRC and LVS is clean we move forward and do the parasitic R and C extraction. Then we go towards physical verification steps like IR Drop analysis, Electro Migration analysis, Antenna checks etc. Once all the verification steps are done properly we will move to electrical and timing characterization and ready for the delivery. If it is a analog block then it will be delivered as a analog IP and if its a analog chip the GDSII file is delivered to the foundry.
Fig 1. Analog and ASIC/SOC Design Flow
Now lets discuss the digital design steps. After front end steps the synthesized netlist is moved to the pre-layout static timing analysis. Now we enter back end.First we do Floor Planning and PnR i.e Place and Route. Floor planning is keeping different blocks at different place and do the area budgeting. Then we do placement of these blocks and do the metal routing and connectivity. Then we do DRC and LVS check on the layout that has come out of the Floor-Plan and Routing stage. Then we do the parasitic RC extraction. Then we proceed towards the STA and Physical Verification. This STA is Post-Layout STA. In physical verification we do IR Drop analysis, EM analysis,Antenna Rule Check etc. Next comes Formal verification and sign off.
So in both analog and SoC Design DRC is equally important and a design be it analog or digital need to be DRC clean before going for fabrication.
Different Mask Layers :
Fig 2. Different Mask Layers in layout
Now let's see what are the various mask layers are used to create layout on the silicon wafer. Layout is nothing but layout of the mask on the wafer. Each part is created with single mask . Metal layers like Metal 1, Metal 2, Metal 3, Metal 4 and we can go upto layers permitted in that particular technology node. Then we can have different types of Well (n and p) and Poly (gate). Then we can have the contact as Cont layer and Via. Via is used to connect two metal layers in routing or BEOL stage and cont is used as source or drain contact.Cont is at FEOL layer. If you want to understand FEOL and BEOL in detail read our article on this topic. Then comes active
layers like ndiff, pdiff, nfet and pfet. Then select layers (n+ and p+) are also present there.
CMOS Fabrication :
Fig 3(a)
Fig 3(b)
Fig 3(c)
Lets see how a PMOS and NMOS are fabricated and connected to built the CMOS. From above three figures we can see MOS is fabricated in layer by layer using different masks. Its done in batch process i.e, when Metal 1 is fabricated , it is done across the whole chip. Similarly all the other layers are fabricated.
For PMOS there is N-well and P -select whereas for NMOS there is N-select. Inside N and P select diffusion layers and Source and Drain contacts are created as shown in Fig 3a. Before creating contacts all the steps involved are in FEOL. After that Poly gates are created and connected with each other see Fig 3b. At final steps Vdd, GND and Vout connections are created see Fig 3c. Connection between transistors , Source or Drain contact creation and Poly gate creation and connection all are included in MEOL. Any step beyond output contact creation is included in BEOL.
Sequence of Mask Layer :
Fig 4. Different Mask Layers
Above figure shows how the mask sequence is introduced in the CMOS fabrication process. It is a typical example we are using to discuss the topic. The above figure shows the sequence starting from N-well, Poly, N+ diffusion, P+ diffusion, Contacts and then Metl layers. So this way sequentially the layers are picked up from the layout and fabricated on the Silicon wafer.
Design Rules :
Each semiconductor process step imposes a set of design rules on the geometric component size, relative position, etc. These rules have subtle differences however the common theme remains the same, mainly to use the proper geometric shape and separation to create a reliable manufacturing process. Some Rules are :
2. Inter-layer: enclosures, overlaps, Separation between 2 wires on same level
3. Width of wires
4. Contact pad for Vias, Well and substrate contacts
5. Cross section of Vias
6. Size of Wells
7. Area, antenna rules, density rules
Antenna rule is a separate topic. If you want to know in detail about Antenna Rule read this article or watch video lecture here.
Classification of Design Rules :
If we classify based on unit, design rules are Micron rules and Lambda rules. On the other hand if we classify based on spacing,there are Inter-layer rule and Intra-layer rule.Inter layer rules are for two different layers regarding spacing between them and all. Intra-layer rules are for same layer segment .
1. Micron Rules : Here, the layout constraints, such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers or nanometers.
2. Lambda Rules : Here, the layout constraints are expressed in terms of a single parameter λ. Hence allow linear and proportional scaling of all geometrical constraints.
So Micron rule is a absolute rule and lambda rule is a relative rule.
So lets summaries the whole discussion.
So far we know,
1. All Design Rules are Predefined by Foundry.
2.Design Rules are Available through Design Rule Manual (DRM) in text/ASCII format.
3. Design Rules are Interpreted by Any Physical Verification
Tool through TCL Coding or Tool-Specific Propitiatory
Language.
4. Layout Tools may have On-The-Fly Live DRC Check during layout Drawing.
5.To understand any DRC Violation we need to cross-reference DRC-Rule-Code and DRM.
In this article we will discuss Antenna Effect and ways to mitigate it. Antenna Effect is a physical phenomenon and related to geometry and fabrication process of the IC. So we will start with vertical cross section of an IC.
The above fig is showing the vertical cross section of a chip and which layer is included in which EOL.
That will help you to relate the EOLs and layers.Now lets discuss about End of Lines.
The whole CMOS fabrication process is divided into :
i. FEOL or Front End of Line :
In First End of Line we develop transistor level layout design on the wafer. The individual components like transistors , capacitors, resistors, etc. are fabricated in the semiconductor. FEOL consist of chemical mechanical polishing a.k.a Polarization and Cleaning of the wafer. Shallow Trench Isolation (STI) or LOCOS (tech node > 0.25 μm) comes under FEOL. FEOL also include well formation , gate module formation, Source and Drain module formation.
ii. MEOL or Mid End of Line :
In Middle End of Line or MEOL we do the transistor level interconnect. MEOL consist of semiconductor wafer processing steps that create local electrical connections among source/drain/gate of transistors. Most important part of MEOL is gate contact formation. Most important part of MEOL is gate contact formation. It occurs after Front-End-Of-Line (i.e transistors/design-capacitor/design-resistor formation) process are complete. Before Back-End-Of-Line metal/via/isolation-dielectric formation processes.
iii. BEOL or Back End of Line :
In Back End of Line we do the PnR level Interconnect through Metalization/Vias including Dielectric Separators among Various Metal layers.
Antenna Effect Phenomenon :
Let's understand what is antenna effect phenomenon. Now-a-days chemical etching has been completely replaced by hot plasma-etching.Plasma related process are used for CMOS flow for etching and deposition. The gaseous plasma contains charged particles inside. This charge gets transferred to the under-construction floating metals routes which may be connected way below up to the gate areas of MOSFET. At the same time such metals may not be connected to any diffusion areas in the FEOL Zone. Such metal wires act as “antennas” charge receptors that pick up electrical charge from the plasma gas. Charge accumulation on the metal strip is proportional to its length.
Now lets understand the antenna phenomenon during the process. As we can see from the above Fig, in the substrate Source (S) , Drain (D) , STI (Shallow Trench Isolation) is formed. Gate Oxide (G) and Poly Silicon layers grown and connected to Metal layer 1(M1). After the metal deposition the layer is etched as per mask. To do that plasma is used for etching. In this gaseous environment many charge get accumulated on the top of the M1 layer. Once this amount of charges is sufficiently high it causes breakdown of Gate Oxide insulator and the charges pass on to the Silicon substrate.
Now we will dig deeper into the phenomenon and will try to understand it in a better way. Aforementioned metal wires builds up high potential difference on the metal side through piled up charge. As a consequence high electric field builds up across the gate oxide of the Metal-Oxide-Semiconductor (MOS) structure.Sufficient accumulation charge create a percussion path through oxide for drainage of charge. This percussion path is a small path that is created by the high amount of charge and this is just the beginning. Severe drainage in MOSFET lead to the gate oxide break-down, consequently damaging the MOSFET. On the other hand in case less severe drainage the MOSFET is not damaged, although Hot Carrier Injection (HCI) may take place. HCI will cause faster aging and MOSFET performance will get degraded in the long run.
Semiconductor CMOS Process :
Antenna violation occurs due to use of plasma in CMOS fabrication. SO let's take a recap of the fabrication steps. The fabrication process of VLSI Integrated Circuits (IC) consists of a set of basic steps starting from crystal growth, wafer preparation, epitaxy, dielectric and poly Si film deposition, oxidation, lithography, and dry etching. Different patterns are developed by repeating steps like deposition, photo resist coating, exposure, developing, etching, ion implantation and stripping etc as shown in the above Fig. These steps are repeated in cyclic order several times for formation of metal routes in the BEOL region. FEOL and MEOL also goes in this cyclic steps although BEOL goes several times. The step etching is done by using plasma and in this step antenna violation may occur. Not only 1st Metal layer, this violation may occur to any metal layer.
Different Types of Plasma Process :
There are three different plasma process involved in VLSI
CMOS process -
1. Conductor Layer Pattern Etching Processes
2. Ashing Processes
3. Contact Etching Processes
1. Conductor Layer Pattern Etching Processes :
Etching processes splits conductor layer plates into multiple routing patterns.Here the amount of accumulated charge is proportional to the perimeter length of conductor area. Perimeters of the spitted routing are directly exposed to plasma.
2. Ashing Processes :
Ashing processes remove remaining photo resist layer after etching processes of conductor layer.Here the amount of accumulated charge is proportional to the area of the conductor layer patterns. Area of conductor layer patterns is directly exposed to plasma.
3. Contact Etching Processes:
Contact etching processes dig holes between two conductor layers. Here the amount of accumulated charge is proportional to the area of the total area of the contacts. Here the area of all the contacts on the lower conductor layer pattern is directly exposed to plasma.
Metals/Via Stacks are built layer by layer. First, Metal1 is deposited and all unwanted portions are etched away by plasma etching. The metal geometries when they are exposed to plasma can collect charge from it. Once Metal1 is completed, Via1 is built, then Metal2 and so on. So with each passing stage, the metal geometries can build up static electricity. If the charge collected is large enough to cause current to flow to the gate, this can cause damage to the gate oxide. Long metal lines are prone to such failures ending into fabrication yield.
Nonuniform density of plasma across the wafer plays an important role in antenna related damage. Such non-uniformity can come from non-uniformity in radio frequency (RF) current flow, electron current flow and ion current flow. In addition to this , Electron shading effect can contribute in plasma charging. This plasma charging(metal) & discharging(through oxide) can severely degrade or destroy devices, especially Metal Oxide Semiconductor (MOS) gate dielectrics. This particular problem is becoming more prominent in lower technology node with thinner gate oxide. The gate oxide degradation occurs by Fowler-Nordheim (FN) tunnel injection between the gate oxide and the silicon substrate.
In the continuous plasma exposure environment, the gate potential build-up adjusts itself by the FN tunneling current. The flow of tunneling current generates trap and interface states in the gate oxide, gradually degrading the oxide quality and integrity. At very high level of stress or prolonged exposure, it may also ultimately lead to the breakdown of the oxide. In high-aspect ratio spaces, isotropic electrons are hindered from reaching the bottom of the space, whereas anisotropic and positively charged ions are not. This is phenomenon is called "electron shading" which happens in uniform plasma when topography exists on the wafer during plasma exposure.Insulators such as photo-resist or oxides are commonly used as masks when etching conductive films. The underlying conductor can acquire a positive charge by the electron shading mechanism.
Antenna Ratio :
The magnitude of the accumulated charge depends on the ratio of the floating conducting region area to the gate area. This is called the Antenna Ratio and quoted in Design Rule Manual.
The above equation shows the relationship between the antenna ratio and the current densities. A higher antenna ratio means a larger Vg and, thus more damage.
Antenna Issue Mitigation :
There are a few ways to to eliminate the antenna effect.
1. Jumper Insertion :
This is creating a metal bridge (a.k.a jumper) near gate of MOS device so that while fabrication. This jumper should take gate connections directly up to the top level metal
through stacked vias. Consequently the gate will not see any antenna due to the break-up of a long metal piece into stacked metal/via layers. The drawback is the use of stacked vias can lead to routing congestion, and hence also to an increase in die area. Stacked metal/vias may/may-not lead to EM/IR reliability issues.
2. Gate Protection Diode:
Here we connect each gate to reverse biased p-n diodes.
Using diode provides a discharge path directly to the substrate by contact to a diffusion area. If possible, these diodes are connected to gate with Metal1 so that prevention starts right with Metal1 fabrication. During normal operation this reverse biased diode will not effect functionality.
However the plasma-induced charge is discharged through the diodes, leaving gate unaffected. Drawback is usage of antenna diodes increase die area by 4-6%.
3. Embedded Protection Diode:
Add protection diodes on every input port for every standard cell. These diodes are embedded and fixed. Hence consume unnecessary area.
4. Diode Insertion After PnR:
Fixing only the wire with the antenna violation which will not waste routing resources. During wafer manufacturing, all the inserted diodes are floating (or ground). One diode can be used to protect all input ports that are connected to the same
In this article we will discuss about Full and Semi custom IC designs. Depending on designing procedure overall VLSI design is grossly classified into two : Full Custom and Semi Custom design. Further Semi Custom ICs are of below types: i. Analog Array ii. Gate Array iii. Standard Cell IC iv. Programmable IC Programmable IC again divided into : i. PLDs ii. PROM iii. PLA iv. PGA v. FPGA
Now let's get an overview of different type of ICs.
I.Full Custom ICs :
The designs which are to be fabricated in extremely super-high-volumes and intended for high volume of sales are
suitable for Full Customs ASICs. Under some special conditions Full Custom ASICs design is followed.
Few of such conditions are :
1. There is no suitable existing libraries available.
2. Existing libraries are not fast enough.
3. Available Pre-designed & Characterized cells consume too much power or area w.r.to the intended design.
Now lets' see how Full Custom Design is done. In Full Custom Design a chip is designed from scratch. Hence time
taken to design IC is longer. All of the logic cells, circuits, and the chip layout are handcrafted by Design
Engineers. Here each individual transistor and the interconnections between them are designed by hand. Mask layers are created by hand in order to fabricate a full-custom IC. Chip Performance maximized and area is minimized at
the cost of human-labor-hours. Full-custom ICs are the most expensive to manufacture and to design.
Advantages :
i. Complete design flexibility
ii. High degree of Power Performance Area (PPA) optimization
iii. Smallest die size
Disadvantages:
i. Large amount of design effort required
ii. Expensive
Example : Microprocessor, Sensors and Actuators, Analog-
Digital Mixed Signal Communication Chips.
II. Semi-Custom ICs :
In Semi-Custom ASIC design a portion of the circuit function is predefined and unalterable, while other portions
are alterable as per need. Pre-designed, Pre-tested and Pre-characterized Standard Cell Libraries or Preconfigured
Arrays are heavily used in such design. Other mega-blocks , such as Micro-controller or Microprocessors, are full-custom
blocks. Many other ready-to-cook blocks , such as System-Level Macros (SLM) , Functional Standard Blocks (FSBs) and IP-Cores are also available to add into the chip making recipe. In the chip layout, location of the building blocks and wiring between them is fully customized through Physical Design. Reusable cell library reduces human effort for a design closure before tape-out. Consequently Semi-Custom ASICs are the less expensive for production.
Advantages:
Time and Money saver & Reduce The risk associated with
full-custom design.
Disadvantages:
Long Manufacture Time & High Non-Recurring-Engineering (NRE) cost.
Examples :
Ethernet Chip, Hard Disk Controller.
III. Gate Array:
Identical cells are Pre-fabricated in the form of Two Dimensional Array on a Gate-Array. Parts of the chip are Pre-Fabricated. Rest of the chip are custom fabricated for any intended design.
There are two types of gate arrays :
i. Channeled Gate Array
ii. Channel-less Gate Array (Sea-of-Gates Array)
In Channeled Gate Arrays, empty spaces are set aside between the base cells to accommodate the wires.
In Channel-Less Gate Array, no such predefined spaces are set aside for routing between the cells.
Interconnection wiring are done above the cells.
Advantages:
Cost saving due to identical structure.
Disadvantages:
Performance is not at per Full-Custom or Standard-Cell-Based ASICs.
IV. Programmable Logic Devices (PLDs):
A PLD is a ready to cook chip-block for implementing logic circuitry. Transistors and Wires are already Pre-exsisting
on it. Logic cells and interconnect can be programmed by end-user to implement specific design. No need to create
custom masks for each customer. Depending on capacity, complexity and architecture, may be further classified as:
i. Simple PLDs (SPLDs),
ii. Complex PLDs (CPLDs)
iii. Field-Programmable Gate Arrays (FPGAs).
Advantages:
Used for low-volume production with Non-Recurring-Engineering Cost, Fast Turnaround Time (TAT).
Disadvantages:
Larger Chip Size , Lower Performance.
V. PLA/SPLD , PAL , CPLD :
1. Programmable Logic Array (PLA a.k.a SPLD):
Here logic functions can be realized in Sum-of-
Products(SOP) form. A programmable AND array
followed by a programmable OR array.
2. Programmable Array Logic Device (PAL) :
A device similar to PLA with improvement on its
weaknesses. A programmable AND array followed by a
fixed OR array. Here OR gate Outputs are followed by
Flip-Flops.
3. Complex Programmable Logic Device (CPLD):
A CPLD consist of multiple PAL-like blocks on a single
chip with programmable wiring to connect the blocks.
VI. Field-Programmable Gate Array/ FPGA :
FPGA is a high capacity programmable logic device. FPGA contains array of programmable basic logic cells surrounded
by programmable interconnect. All of these can be configured/programmed by end-user for intended design.
Both combinational and sequential logic are achievable.
Capacity: 1K to 1M logic gates.
Speed: Up to 100MHz.
Popular applications: Prototyping, FPGA-based computers, DSP, logic emulation etc.
Now let's compare them based on PPA, Cost and TAT :
Now let's do engineering comparison :
From above discussion we can draw below conclusions :
Full Custom can give the best packing density inside the
silicon die and performance. It is used for microprocessors and other complex volume applications.
Faster design closure time and lower cost are the key success point of standard cell over full-custom. For large design, it is the best practice to partition the circuit into smaller sub-blocks which are designed using different team.
FPGA may be used for simple and low volume applications.
However, Gate Arrays provide much higher density over FPGA.
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